Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md	(revision 207262)
+++ gcc/config/rs6000/vsx.md	(working copy)
@@ -1678,9 +1679,9 @@
 
 ;; Expanders for builtins
 (define_expand "vsx_mergel_<mode>"
-  [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
-   (use (match_operand:VSX_D 1 "vsx_register_operand" ""))
-   (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]
+  [(match_operand:VSX_D 0 "vsx_register_operand" "")
+   (match_operand:VSX_D 1 "vsx_register_operand" "")
+   (match_operand:VSX_D 2 "vsx_register_operand" "")]
   "VECTOR_MEM_VSX_P (<MODE>mode)"
 {
   rtvec v;
@@ -1700,12 +1701,13 @@
 
   x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_expand "vsx_mergeh_<mode>"
-  [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
-   (use (match_operand:VSX_D 1 "vsx_register_operand" ""))
-   (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]
+  [(match_operand:VSX_D 0 "vsx_register_operand" "")
+   (match_operand:VSX_D 1 "vsx_register_operand" "")
+   (match_operand:VSX_D 2 "vsx_register_operand" "")]
   "VECTOR_MEM_VSX_P (<MODE>mode)"
 {
   rtvec v;
@@ -1725,6 +1727,7 @@
 
   x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 ;; V2DF/V2DI splat
Index: gcc/config/rs6000/altivec.md
===================================================================
--- gcc/config/rs6000/altivec.md	(revision 207262)
+++ gcc/config/rs6000/altivec.md	(working copy)
@@ -843,9 +843,9 @@
   [(set_attr "type" "veccomplex")])
 
 (define_expand "altivec_vmrghb"
-  [(use (match_operand:V16QI 0 "register_operand" ""))
-   (use (match_operand:V16QI 1 "register_operand" ""))
-   (use (match_operand:V16QI 2 "register_operand" ""))]
+  [(match_operand:V16QI 0 "register_operand" "")
+   (match_operand:V16QI 1 "register_operand" "")
+   (match_operand:V16QI 2 "register_operand" "")]
   "TARGET_ALTIVEC"
 {
   rtvec v;
@@ -871,6 +871,7 @@
 
   x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrghb_internal"
@@ -906,9 +907,9 @@
   [(set_attr "type" "vecperm")])
 
 (define_expand "altivec_vmrghh"
-  [(use (match_operand:V8HI 0 "register_operand" ""))
-   (use (match_operand:V8HI 1 "register_operand" ""))
-   (use (match_operand:V8HI 2 "register_operand" ""))]
+  [(match_operand:V8HI 0 "register_operand" "")
+   (match_operand:V8HI 1 "register_operand" "")
+   (match_operand:V8HI 2 "register_operand" "")]
   "TARGET_ALTIVEC"
 {
   rtvec v;
@@ -930,6 +931,7 @@
 
   x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrghh_internal"
@@ -961,9 +963,9 @@
   [(set_attr "type" "vecperm")])
 
 (define_expand "altivec_vmrghw"
-  [(use (match_operand:V4SI 0 "register_operand" ""))
-   (use (match_operand:V4SI 1 "register_operand" ""))
-   (use (match_operand:V4SI 2 "register_operand" ""))]
+  [(match_operand:V4SI 0 "register_operand" "")
+   (match_operand:V4SI 1 "register_operand" "")
+   (match_operand:V4SI 2 "register_operand" "")]
   "VECTOR_MEM_ALTIVEC_P (V4SImode)"
 {
   rtvec v;
@@ -983,6 +985,7 @@
 
   x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrghw_internal"
@@ -1029,9 +1032,9 @@
   [(set_attr "type" "vecperm")])
 
 (define_expand "altivec_vmrglb"
-  [(use (match_operand:V16QI 0 "register_operand" ""))
-   (use (match_operand:V16QI 1 "register_operand" ""))
-   (use (match_operand:V16QI 2 "register_operand" ""))]
+  [(match_operand:V16QI 0 "register_operand" "")
+   (match_operand:V16QI 1 "register_operand" "")
+   (match_operand:V16QI 2 "register_operand" "")]
   "TARGET_ALTIVEC"
 {
   rtvec v;
@@ -1057,6 +1060,7 @@
 
   x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrglb_internal"
@@ -1092,9 +1096,9 @@
   [(set_attr "type" "vecperm")])
 
 (define_expand "altivec_vmrglh"
-  [(use (match_operand:V8HI 0 "register_operand" ""))
-   (use (match_operand:V8HI 1 "register_operand" ""))
-   (use (match_operand:V8HI 2 "register_operand" ""))]
+  [(match_operand:V8HI 0 "register_operand" "")
+   (match_operand:V8HI 1 "register_operand" "")
+   (match_operand:V8HI 2 "register_operand" "")]
   "TARGET_ALTIVEC"
 {
   rtvec v;
@@ -1116,6 +1120,7 @@
 
   x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrglh_internal"
@@ -1147,9 +1152,9 @@
   [(set_attr "type" "vecperm")])
 
 (define_expand "altivec_vmrglw"
-  [(use (match_operand:V4SI 0 "register_operand" ""))
-   (use (match_operand:V4SI 1 "register_operand" ""))
-   (use (match_operand:V4SI 2 "register_operand" ""))]
+  [(match_operand:V4SI 0 "register_operand" "")
+   (match_operand:V4SI 1 "register_operand" "")
+   (match_operand:V4SI 2 "register_operand" "")]
   "VECTOR_MEM_ALTIVEC_P (V4SImode)"
 {
   rtvec v;
@@ -1169,6 +1174,7 @@
 
   x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));
   emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
+  DONE;
 })
 
 (define_insn "*altivec_vmrglw_internal"
