From patchwork Thu Jan 30 16:34:56 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 315408 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8569E2C00AB for ; Fri, 31 Jan 2014 03:35:11 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=I+0 4z29eMjm2kY+8VyZtV7Zuhqx7QPgRYOHVRvAImJkr2KUpS/J6sBFzvBVG35DL0pv rJToMZiB9aJiujdeEE29TXWW/K6Gbi+s+f4KxnFTJruqt3zMzMRTIW59OFcy8yDk jexNjTLikjQOLtWFc9u1xNuV1w9x2uI3OwhUkPFw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; s=default; bh=MAPN3LTSY xajbQICGDr8YGWDozs=; b=eo/scM8uAcdv8RLhJOw6u4ttS99wg0QEVNYyn0oH2 oyD6s1EUt/wlvjVg0kuezTrfIye68sSkrSptaz47EifD+qXMkG8GRAEyV2VNbB3S K0CAanaQXF3NsbI4wAHEz8prtgX7R4x9LcYWdLtdOMCXVKAjhaoXJAYdCwLkWkxM S8= Received: (qmail 9306 invoked by alias); 30 Jan 2014 16:35:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9294 invoked by uid 89); 30 Jan 2014 16:35:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.7 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e28smtp08.in.ibm.com Received: from e28smtp08.in.ibm.com (HELO e28smtp08.in.ibm.com) (122.248.162.8) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 30 Jan 2014 16:35:00 +0000 Received: from /spool/local by e28smtp08.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 30 Jan 2014 22:04:52 +0530 Received: from d28relay04.in.ibm.com (d28relay04.in.ibm.com [9.184.220.61]) by d28dlp01.in.ibm.com (Postfix) with ESMTP id D6A25E0057 for ; Thu, 30 Jan 2014 22:07:59 +0530 (IST) Received: from d28av05.in.ibm.com (d28av05.in.ibm.com [9.184.220.67]) by d28relay04.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s0UGYqlD43057234 for ; Thu, 30 Jan 2014 22:04:52 +0530 Received: from d28av05.in.ibm.com (localhost [127.0.0.1]) by d28av05.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s0UGYp2L026183 for ; Thu, 30 Jan 2014 22:04:51 +0530 Received: from [9.65.3.207] (sig-9-65-3-207.mts.ibm.com [9.65.3.207]) by d28av05.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s0UGYmsP026114; Thu, 30 Jan 2014 22:04:50 +0530 Message-ID: <1391099696.28411.32.camel@gnopaine> Subject: [PATCH, rs6000] Clean up mergeh/mergel patterns to avoid missed optimizations From: Bill Schmidt To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com Date: Thu, 30 Jan 2014 10:34:56 -0600 Mime-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14013016-2000-0000-0000-00000F84EDA3 X-IsSubscribed: yes Hi, When I implemented the mergeh/mergel code for -maltivec=be, I forgot to add DONE; at the end of the define_expands, leading to spurious "use" rtx's in the RTL stream. I discovered this while testing some other code, where a similar problem resulted in some missed optimizations. This patch fixes the issue. As a side note, I had copied existing patterns that wrapped the "match_operand"s in "use"s, but I don't see any reason for that in retrospect, so I removed the "use"s altogether. Bootstrapped and tested on powerpc64{,le}-unknown-linux-gnu with no regressions. Ok for trunk? Thanks, Bill 2014-01-30 Bill Schmidt * config/rs6000/vsx.md (vsx_mergel_): Remove "use" specifications; add DONE. (vsx_mergeh_): Likewise. * config/rs6000/altivec.md (altivec_vmrghb): Likewise. (altivec_vmrghh): Likewise. (altivec_vmrghw): Likewise. (altivec_vmrglb): Likewise. (altivec_vmrglh): Likewise. (altivec_vmrglw): Likewise. Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md (revision 207262) +++ gcc/config/rs6000/vsx.md (working copy) @@ -1678,9 +1679,9 @@ ;; Expanders for builtins (define_expand "vsx_mergel_" - [(use (match_operand:VSX_D 0 "vsx_register_operand" "")) - (use (match_operand:VSX_D 1 "vsx_register_operand" "")) - (use (match_operand:VSX_D 2 "vsx_register_operand" ""))] + [(match_operand:VSX_D 0 "vsx_register_operand" "") + (match_operand:VSX_D 1 "vsx_register_operand" "") + (match_operand:VSX_D 2 "vsx_register_operand" "")] "VECTOR_MEM_VSX_P (mode)" { rtvec v; @@ -1700,12 +1701,13 @@ x = gen_rtx_VEC_SELECT (mode, x, gen_rtx_PARALLEL (VOIDmode, v)); emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; }) (define_expand "vsx_mergeh_" - [(use (match_operand:VSX_D 0 "vsx_register_operand" "")) - (use (match_operand:VSX_D 1 "vsx_register_operand" "")) - (use (match_operand:VSX_D 2 "vsx_register_operand" ""))] + [(match_operand:VSX_D 0 "vsx_register_operand" "") + (match_operand:VSX_D 1 "vsx_register_operand" "") + (match_operand:VSX_D 2 "vsx_register_operand" "")] "VECTOR_MEM_VSX_P (mode)" { rtvec v; @@ -1725,6 +1727,7 @@ x = gen_rtx_VEC_SELECT (mode, x, gen_rtx_PARALLEL (VOIDmode, v)); emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; }) ;; V2DF/V2DI splat Index: gcc/config/rs6000/altivec.md =================================================================== --- gcc/config/rs6000/altivec.md (revision 207262) +++ gcc/config/rs6000/altivec.md (working copy) @@ -843,9 +843,9 @@ [(set_attr "type" "veccomplex")]) (define_expand "altivec_vmrghb" - [(use (match_operand:V16QI 0 "register_operand" "")) - (use (match_operand:V16QI 1 "register_operand" "")) - (use (match_operand:V16QI 2 "register_operand" ""))] + [(match_operand:V16QI 0 "register_operand" "") + (match_operand:V16QI 1 "register_operand" "") + (match_operand:V16QI 2 "register_operand" "")] "TARGET_ALTIVEC" { rtvec v; @@ -871,6 +871,7 @@ x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v)); emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; }) (define_insn "*altivec_vmrghb_internal" @@ -906,9 +907,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vmrghh" - [(use (match_operand:V8HI 0 "register_operand" "")) - (use (match_operand:V8HI 1 "register_operand" "")) - (use (match_operand:V8HI 2 "register_operand" ""))] + [(match_operand:V8HI 0 "register_operand" "") + (match_operand:V8HI 1 "register_operand" "") + (match_operand:V8HI 2 "register_operand" "")] "TARGET_ALTIVEC" { rtvec v; @@ -930,6 +931,7 @@ x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v)); emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; }) (define_insn "*altivec_vmrghh_internal" @@ -961,9 +963,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vmrghw" - [(use (match_operand:V4SI 0 "register_operand" "")) - (use (match_operand:V4SI 1 "register_operand" "")) - (use (match_operand:V4SI 2 "register_operand" ""))] + [(match_operand:V4SI 0 "register_operand" "") + (match_operand:V4SI 1 "register_operand" "") + (match_operand:V4SI 2 "register_operand" "")] "VECTOR_MEM_ALTIVEC_P (V4SImode)" { rtvec v; @@ -983,6 +985,7 @@ x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v)); emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; }) (define_insn "*altivec_vmrghw_internal" @@ -1029,9 +1032,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vmrglb" - [(use (match_operand:V16QI 0 "register_operand" "")) - (use (match_operand:V16QI 1 "register_operand" "")) - (use (match_operand:V16QI 2 "register_operand" ""))] + [(match_operand:V16QI 0 "register_operand" "") + (match_operand:V16QI 1 "register_operand" "") + (match_operand:V16QI 2 "register_operand" "")] "TARGET_ALTIVEC" { rtvec v; @@ -1057,6 +1060,7 @@ x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v)); emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; }) (define_insn "*altivec_vmrglb_internal" @@ -1092,9 +1096,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vmrglh" - [(use (match_operand:V8HI 0 "register_operand" "")) - (use (match_operand:V8HI 1 "register_operand" "")) - (use (match_operand:V8HI 2 "register_operand" ""))] + [(match_operand:V8HI 0 "register_operand" "") + (match_operand:V8HI 1 "register_operand" "") + (match_operand:V8HI 2 "register_operand" "")] "TARGET_ALTIVEC" { rtvec v; @@ -1116,6 +1120,7 @@ x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v)); emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; }) (define_insn "*altivec_vmrglh_internal" @@ -1147,9 +1152,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vmrglw" - [(use (match_operand:V4SI 0 "register_operand" "")) - (use (match_operand:V4SI 1 "register_operand" "")) - (use (match_operand:V4SI 2 "register_operand" ""))] + [(match_operand:V4SI 0 "register_operand" "") + (match_operand:V4SI 1 "register_operand" "") + (match_operand:V4SI 2 "register_operand" "")] "VECTOR_MEM_ALTIVEC_P (V4SImode)" { rtvec v; @@ -1169,6 +1174,7 @@ x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v)); emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; }) (define_insn "*altivec_vmrglw_internal"