From patchwork Mon Jan 13 23:37:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 310411 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8C3442C0089 for ; Tue, 14 Jan 2014 10:37:59 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=ftx zeyqzewzEMm2n6o2x+f079ysVlgbjziBsD05ttxguXnWJ4rZJTn3p5D16cFb0wH2 GemlhaUF4R3JcV45vL1Io3U/uYdho/NexS0RncH2FTj+Vg5yR9yTxQALtew09puJ csfoeSAuac6uVAQjaO7Bd52r0mvZRv98lt5uKJQ8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; s=default; bh=WqIipH6Wj sW9PZBLmNqtJFHoXGM=; b=TxJkx6kZ4Pnv/vicQaMY/pIttL1GNdR3Ty+E5FyV0 QQi/wh2yygG9HFmMkoV/xvlaQ7pTf3VMVAtGIdPTXioDPlEHLHEZZEEIWT1xvvvP 09SyP8xx/BD/9Bwd/LP9/O9niR7UOsAcLcjLgb4KRIFggyqgxcPfj+HH5sXndy7K fc= Received: (qmail 13386 invoked by alias); 13 Jan 2014 23:37:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 13371 invoked by uid 89); 13 Jan 2014 23:37:50 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e28smtp09.in.ibm.com Received: from e28smtp09.in.ibm.com (HELO e28smtp09.in.ibm.com) (122.248.162.9) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Mon, 13 Jan 2014 23:37:48 +0000 Received: from /spool/local by e28smtp09.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 14 Jan 2014 05:07:41 +0530 Received: from d28relay01.in.ibm.com (d28relay01.in.ibm.com [9.184.220.58]) by d28dlp01.in.ibm.com (Postfix) with ESMTP id 6693DE0053 for ; Tue, 14 Jan 2014 05:10:32 +0530 (IST) Received: from d28av03.in.ibm.com (d28av03.in.ibm.com [9.184.220.65]) by d28relay01.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s0DNbaYG56164550 for ; Tue, 14 Jan 2014 05:07:37 +0530 Received: from d28av03.in.ibm.com (localhost [127.0.0.1]) by d28av03.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s0DNbed5028934 for ; Tue, 14 Jan 2014 05:07:40 +0530 Received: from [9.57.79.178] ([9.57.79.178]) by d28av03.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s0DNbblH028906; Tue, 14 Jan 2014 05:07:38 +0530 Message-ID: <1389656268.18332.33.camel@gnopaine> Subject: [PATCH, rs6000] Implement -maltivec=be for vec_mule and vec_mulo Altivec intrinsics From: Bill Schmidt To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com Date: Mon, 13 Jan 2014 17:37:48 -0600 Mime-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14011323-2674-0000-0000-00000C444CB8 X-IsSubscribed: yes This patch provides for interpreting parity of element numbers for the Altivec vec_mule and vec_mulo intrinsics as big-endian (left to right in a vector register) when targeting a little endian machine and specifying -maltivec=be. New test cases are added to test this functionality on all supported vector types. The main change is in the altivec.md define_insns for vec_widen_{su}mult_{even,odd}_{v8hi,v16qi}, where we now test for VECTOR_ELT_ORDER_BIG rather than BYTES_BIG_ENDIAN in order to treat the element order as big-endian. However, this necessitates changes to other places in altivec.md where we previously called gen_vec_widen_{su}mult_*. The semantics of these internal uses are not affected by -maltivec=be, so these are now replaced with direct generation of the underlying instructions that were previously generated. Bootstrapped and tested with no new regressions on powerpc64{,le}-unknown-linux-gnu. Ok for trunk? Thanks, Bill gcc: 2014-01-13 Bill Schmidt * config/rs6000/altivec.md (mulv8hi3): Explicitly generate vmulesh and vmulosh rather than call gen_vec_widen_smult_*. (vec_widen_umult_even_v16qi): Test VECTOR_ELT_ORDER_BIG rather than BYTES_BIG_ENDIAN to determine use of even or odd instruction. (vec_widen_smult_even_v16qi): Likewise. (vec_widen_umult_even_v8hi): Likewise. (vec_widen_smult_even_v8hi): Likewise. (vec_widen_umult_odd_v16qi): Likewise. (vec_widen_smult_odd_v16qi): Likewise. (vec_widen_umult_odd_v8hi): Likewise. (vec_widen_smult_odd_v8hi): Likewise. (vec_widen_umult_hi_v16qi): Explicitly generate vmuleub and vmuloub rather than call gen_vec_widen_umult_*. (vec_widen_umult_lo_v16qi): Likewise. (vec_widen_smult_hi_v16qi): Explicitly generate vmulesb and vmulosb rather than call gen_vec_widen_smult_*. (vec_widen_smult_lo_v16qi): Likewise. (vec_widen_umult_hi_v8hi): Explicitly generate vmuleuh and vmulouh rather than call gen_vec_widen_umult_*. (vec_widen_umult_lo_v8hi): Likewise. (vec_widen_smult_hi_v8hi): Explicitly gnerate vmulesh and vmulosh rather than call gen_vec_widen_smult_*. (vec_widen_smult_lo_v8hi): Likewise. gcc/testsuite: 2014-01-13 Bill Schmidt * gcc.dg/vmx/mult-even-odd.c: New. * gcc.dg/vmx/mult-even-odd-be-order.c: New. Index: gcc/testsuite/gcc.dg/vmx/mult-even-odd.c =================================================================== --- gcc/testsuite/gcc.dg/vmx/mult-even-odd.c (revision 0) +++ gcc/testsuite/gcc.dg/vmx/mult-even-odd.c (revision 0) @@ -0,0 +1,43 @@ +#include "harness.h" + +static void test() +{ + vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3}; + vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7}; + vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3}; + vector unsigned short vusa = {0,1,2,3,4,5,6,7}; + vector unsigned short vusb = {2,3,2,3,2,3,2,3}; + vector signed short vssa = {-4,-3,-2,-1,0,1,2,3}; + vector signed short vssb = {2,-3,2,-3,2,-3,2,-3}; + vector unsigned short vuse, vuso; + vector signed short vsse, vsso; + vector unsigned int vuie, vuio; + vector signed int vsie, vsio; + + vuse = vec_mule (vuca, vucb); + vuso = vec_mulo (vuca, vucb); + vsse = vec_mule (vsca, vscb); + vsso = vec_mulo (vsca, vscb); + vuie = vec_mule (vusa, vusb); + vuio = vec_mulo (vusa, vusb); + vsie = vec_mule (vssa, vssb); + vsio = vec_mulo (vssa, vssb); + + check (vec_all_eq (vuse, + ((vector unsigned short){0,4,8,12,16,20,24,28})), + "vuse"); + check (vec_all_eq (vuso, + ((vector unsigned short){3,9,15,21,27,33,39,45})), + "vuso"); + check (vec_all_eq (vsse, + ((vector signed short){-16,-12,-8,-4,0,4,8,12})), + "vsse"); + check (vec_all_eq (vsso, + ((vector signed short){21,15,9,3,-3,-9,-15,-21})), + "vsso"); + check (vec_all_eq (vuie, ((vector unsigned int){0,4,8,12})), "vuie"); + check (vec_all_eq (vuio, ((vector unsigned int){3,9,15,21})), "vuio"); + check (vec_all_eq (vsie, ((vector signed int){-8,-4,0,4})), "vsie"); + check (vec_all_eq (vsio, ((vector signed int){9,3,-3,-9})), "vsio"); +} Index: gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c =================================================================== --- gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c (revision 0) +++ gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c (revision 0) @@ -0,0 +1,64 @@ +/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */ + +#include "harness.h" + +static void test() +{ + vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3}; + vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7}; + vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3}; + vector unsigned short vusa = {0,1,2,3,4,5,6,7}; + vector unsigned short vusb = {2,3,2,3,2,3,2,3}; + vector signed short vssa = {-4,-3,-2,-1,0,1,2,3}; + vector signed short vssb = {2,-3,2,-3,2,-3,2,-3}; + vector unsigned short vuse, vuso; + vector signed short vsse, vsso; + vector unsigned int vuie, vuio; + vector signed int vsie, vsio; + + vuse = vec_mule (vuca, vucb); + vuso = vec_mulo (vuca, vucb); + vsse = vec_mule (vsca, vscb); + vsso = vec_mulo (vsca, vscb); + vuie = vec_mule (vusa, vusb); + vuio = vec_mulo (vusa, vusb); + vsie = vec_mule (vssa, vssb); + vsio = vec_mulo (vssa, vssb); + +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + check (vec_all_eq (vuse, + ((vector unsigned short){3,9,15,21,27,33,39,45})), + "vuse"); + check (vec_all_eq (vuso, + ((vector unsigned short){0,4,8,12,16,20,24,28})), + "vuso"); + check (vec_all_eq (vsse, + ((vector signed short){21,15,9,3,-3,-9,-15,-21})), + "vsse"); + check (vec_all_eq (vsso, + ((vector signed short){-16,-12,-8,-4,0,4,8,12})), + "vsso"); + check (vec_all_eq (vuie, ((vector unsigned int){3,9,15,21})), "vuie"); + check (vec_all_eq (vuio, ((vector unsigned int){0,4,8,12})), "vuio"); + check (vec_all_eq (vsie, ((vector signed int){9,3,-3,-9})), "vsie"); + check (vec_all_eq (vsio, ((vector signed int){-8,-4,0,4})), "vsio"); +#else + check (vec_all_eq (vuse, + ((vector unsigned short){0,4,8,12,16,20,24,28})), + "vuse"); + check (vec_all_eq (vuso, + ((vector unsigned short){3,9,15,21,27,33,39,45})), + "vuso"); + check (vec_all_eq (vsse, + ((vector signed short){-16,-12,-8,-4,0,4,8,12})), + "vsse"); + check (vec_all_eq (vsso, + ((vector signed short){21,15,9,3,-3,-9,-15,-21})), + "vsso"); + check (vec_all_eq (vuie, ((vector unsigned int){0,4,8,12})), "vuie"); + check (vec_all_eq (vuio, ((vector unsigned int){3,9,15,21})), "vuio"); + check (vec_all_eq (vsie, ((vector signed int){-8,-4,0,4})), "vsie"); + check (vec_all_eq (vsio, ((vector signed int){9,3,-3,-9})), "vsio"); +#endif +} Index: gcc/config/rs6000/altivec.md =================================================================== --- gcc/config/rs6000/altivec.md (revision 206375) +++ gcc/config/rs6000/altivec.md (working copy) @@ -673,17 +673,18 @@ rtx high = gen_reg_rtx (V4SImode); rtx low = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_smult_even_v8hi (even, operands[1], operands[2])); - emit_insn (gen_vec_widen_smult_odd_v8hi (odd, operands[1], operands[2])); - if (BYTES_BIG_ENDIAN) { + emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2])); + emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2])); emit_insn (gen_altivec_vmrghw (high, even, odd)); emit_insn (gen_altivec_vmrglw (low, even, odd)); emit_insn (gen_altivec_vpkuwum (operands[0], high, low)); } else { + emit_insn (gen_altivec_vmulosh (even, operands[1], operands[2])); + emit_insn (gen_altivec_vmulesh (odd, operands[1], operands[2])); emit_insn (gen_altivec_vmrghw (high, odd, even)); emit_insn (gen_altivec_vmrglw (low, odd, even)); emit_insn (gen_altivec_vpkuwum (operands[0], low, high)); @@ -981,7 +982,7 @@ (use (match_operand:V16QI 2 "register_operand" ""))] "TARGET_ALTIVEC" { - if (BYTES_BIG_ENDIAN) + if (VECTOR_ELT_ORDER_BIG) emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2])); else emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2])); @@ -994,7 +995,7 @@ (use (match_operand:V16QI 2 "register_operand" ""))] "TARGET_ALTIVEC" { - if (BYTES_BIG_ENDIAN) + if (VECTOR_ELT_ORDER_BIG) emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2])); else emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2])); @@ -1007,7 +1008,7 @@ (use (match_operand:V8HI 2 "register_operand" ""))] "TARGET_ALTIVEC" { - if (BYTES_BIG_ENDIAN) + if (VECTOR_ELT_ORDER_BIG) emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2])); else emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2])); @@ -1020,7 +1021,7 @@ (use (match_operand:V8HI 2 "register_operand" ""))] "TARGET_ALTIVEC" { - if (BYTES_BIG_ENDIAN) + if (VECTOR_ELT_ORDER_BIG) emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2])); else emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2])); @@ -1033,7 +1034,7 @@ (use (match_operand:V16QI 2 "register_operand" ""))] "TARGET_ALTIVEC" { - if (BYTES_BIG_ENDIAN) + if (VECTOR_ELT_ORDER_BIG) emit_insn (gen_altivec_vmuloub (operands[0], operands[1], operands[2])); else emit_insn (gen_altivec_vmuleub (operands[0], operands[1], operands[2])); @@ -1046,7 +1047,7 @@ (use (match_operand:V16QI 2 "register_operand" ""))] "TARGET_ALTIVEC" { - if (BYTES_BIG_ENDIAN) + if (VECTOR_ELT_ORDER_BIG) emit_insn (gen_altivec_vmulosb (operands[0], operands[1], operands[2])); else emit_insn (gen_altivec_vmulesb (operands[0], operands[1], operands[2])); @@ -1059,7 +1060,7 @@ (use (match_operand:V8HI 2 "register_operand" ""))] "TARGET_ALTIVEC" { - if (BYTES_BIG_ENDIAN) + if (VECTOR_ELT_ORDER_BIG) emit_insn (gen_altivec_vmulouh (operands[0], operands[1], operands[2])); else emit_insn (gen_altivec_vmuleuh (operands[0], operands[1], operands[2])); @@ -1072,7 +1073,7 @@ (use (match_operand:V8HI 2 "register_operand" ""))] "TARGET_ALTIVEC" { - if (BYTES_BIG_ENDIAN) + if (VECTOR_ELT_ORDER_BIG) emit_insn (gen_altivec_vmulosh (operands[0], operands[1], operands[2])); else emit_insn (gen_altivec_vmulesh (operands[0], operands[1], operands[2])); @@ -2220,12 +2221,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); - emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2])); if (BYTES_BIG_ENDIAN) - emit_insn (gen_altivec_vmrghh (operands[0], ve, vo)); + { + emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghh (operands[0], ve, vo)); + } else - emit_insn (gen_altivec_vmrghh (operands[0], vo, ve)); + { + emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghh (operands[0], vo, ve)); + } DONE; }") @@ -2240,12 +2247,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); - emit_insn (gen_vec_widen_umult_even_v16qi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_umult_odd_v16qi (vo, operands[1], operands[2])); if (BYTES_BIG_ENDIAN) - emit_insn (gen_altivec_vmrglh (operands[0], ve, vo)); + { + emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglh (operands[0], ve, vo)); + } else - emit_insn (gen_altivec_vmrglh (operands[0], vo, ve)); + { + emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglh (operands[0], vo, ve)); + } DONE; }") @@ -2260,12 +2273,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); - emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2])); if (BYTES_BIG_ENDIAN) - emit_insn (gen_altivec_vmrghh (operands[0], ve, vo)); + { + emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghh (operands[0], ve, vo)); + } else - emit_insn (gen_altivec_vmrghh (operands[0], vo, ve)); + { + emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghh (operands[0], vo, ve)); + } DONE; }") @@ -2280,12 +2299,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); - emit_insn (gen_vec_widen_smult_even_v16qi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_smult_odd_v16qi (vo, operands[1], operands[2])); if (BYTES_BIG_ENDIAN) - emit_insn (gen_altivec_vmrglh (operands[0], ve, vo)); + { + emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglh (operands[0], ve, vo)); + } else - emit_insn (gen_altivec_vmrglh (operands[0], vo, ve)); + { + emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglh (operands[0], vo, ve)); + } DONE; }") @@ -2300,12 +2325,18 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2])); if (BYTES_BIG_ENDIAN) - emit_insn (gen_altivec_vmrghw (operands[0], ve, vo)); + { + emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghw (operands[0], ve, vo)); + } else - emit_insn (gen_altivec_vmrghw (operands[0], vo, ve)); + { + emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghw (operands[0], vo, ve)); + } DONE; }") @@ -2320,12 +2351,18 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2])); if (BYTES_BIG_ENDIAN) - emit_insn (gen_altivec_vmrglw (operands[0], ve, vo)); + { + emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglw (operands[0], ve, vo)); + } else - emit_insn (gen_altivec_vmrglw (operands[0], vo, ve)); + { + emit_insn (gen_altivec_vmulouh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmuleuh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglw (operands[0], vo, ve)); + } DONE; }") @@ -2340,12 +2377,18 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2])); if (BYTES_BIG_ENDIAN) - emit_insn (gen_altivec_vmrghw (operands[0], ve, vo)); + { + emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghw (operands[0], ve, vo)); + } else - emit_insn (gen_altivec_vmrghw (operands[0], vo, ve)); + { + emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrghw (operands[0], vo, ve)); + } DONE; }") @@ -2360,12 +2403,18 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2])); - emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2])); if (BYTES_BIG_ENDIAN) - emit_insn (gen_altivec_vmrglw (operands[0], ve, vo)); + { + emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglw (operands[0], ve, vo)); + } else - emit_insn (gen_altivec_vmrglw (operands[0], vo, ve)); + { + emit_insn (gen_altivec_vmulosh (ve, operands[1], operands[2])); + emit_insn (gen_altivec_vmulesh (vo, operands[1], operands[2])); + emit_insn (gen_altivec_vmrglw (operands[0], vo, ve)); + } DONE; }")