From patchwork Thu Jan 9 18:14:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 308904 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E5D642C00C4 for ; Fri, 10 Jan 2014 05:14:25 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:content-transfer-encoding; q=dns; s= default; b=udWxpdihGfmdspZjaqxBs18+GzTXxDI2a59ypKOKS/jk0ghP85lpr KTKhLuvwtxHHAt4s/xI7RQ8pdO+zL/bjfxciGFbKX6fe4W7OayZhGyoAtjdigBO+ QWRkh/5A9nwARM9scypv12CxVsTHMQcsVyCI6vWONN+F9ZZZHYt3dM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:content-transfer-encoding; s=default; bh=2ENBAvdDx1ZI6QiUIsI0T++cx0c=; b=bg/IdwgdzWElft4ZIrfTRMdimMAn HUlTN7WUyk489xYFzVKLRhhlslh4GM3UAeYwTvOVUCe7R/rAD/s7GHByLWEKsdup QM3fyVfuURS73a9JggLqyTNFAK+vja3PDP/6stnWvGXHZdGMHGDIqmhTwwJeoCT7 i5wkbVatSMONakU= Received: (qmail 21331 invoked by alias); 9 Jan 2014 18:14:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 21322 invoked by uid 89); 9 Jan 2014 18:14:18 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e37.co.us.ibm.com Received: from e37.co.us.ibm.com (HELO e37.co.us.ibm.com) (32.97.110.158) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 09 Jan 2014 18:14:17 +0000 Received: from /spool/local by e37.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 9 Jan 2014 11:14:13 -0700 Received: from b03cxnp07027.gho.boulder.ibm.com (b03cxnp07027.gho.boulder.ibm.com [9.17.130.14]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id 87B441FF001A for ; Thu, 9 Jan 2014 11:13:43 -0700 (MST) Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by b03cxnp07027.gho.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s09IE0mE64553002 for ; Thu, 9 Jan 2014 19:14:00 +0100 Received: from d03av02.boulder.ibm.com (localhost [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s09IECAH023709 for ; Thu, 9 Jan 2014 11:14:12 -0700 Received: from [9.10.86.59] (oc8801110288.ibm.com.rchland.ibm.com [9.10.86.59]) by d03av02.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s09IEBoO023662; Thu, 9 Jan 2014 11:14:11 -0700 Subject: Re: [PATCH,rs6000] Add -maltivec={le,be} options From: Bill Schmidt To: David Edelsohn Cc: "Joseph S. Myers" , GCC Patches In-Reply-To: References: <1389128467.18332.10.camel@gnopaine> <1389132375.18332.18.camel@gnopaine> <1389139166.18332.19.camel@gnopaine> Date: Thu, 09 Jan 2014 12:14:10 -0600 Message-ID: <1389291250.4862.10.camel@oc8801110288.ibm.com> Mime-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14010918-7164-0000-0000-000004F8E7B7 X-IsSubscribed: yes Thanks for the comments! Here is a second go-round at the patch with improved documentation. I'm happy to change the wording if it can be further improved. Thanks, Bill 2014-01-09 Bill Schmidt * doc/invoke.texi: Add -maltivec={be,le} options, and document default element-order behavior for -maltivec. * config/rs6000/rs6000.opt: Add -maltivec={be,le} options. * config/rs6000/rs6000.c (rs6000_option_override_internal): Ensure that -maltivec={le,be} implies -maltivec; disallow -maltivec=le when targeting big endian, at least for now. * config/rs6000/rs6000.h: Add #define of VECTOR_ELT_ORDER_BIG. On Wed, 2014-01-08 at 16:46 -0500, David Edelsohn wrote: > On Tue, Jan 7, 2014 at 6:59 PM, Bill Schmidt > wrote: > > On Tue, 2014-01-07 at 22:18 +0000, Joseph S. Myers wrote: > >> On Tue, 7 Jan 2014, Bill Schmidt wrote: > >> > >> > Yes, sorry for not being more clear. This is indeed for interpretation > >> > of element numbers in Altivec intrinsics such as vec_splat, vec_extract, > >> > vec_insert, and so forth. By default these will match array element > >> > order for the target endianness. But with -maltivec=be for a little > >> > endian target, we will force use of big-endian element order (matching > >> > the behavior of the underlying hardware instructions). > >> > >> Thanks for the explanation. I think you should make the .texi > >> documentation say something more like this. > >> > > > > Sure, I can wordsmith something along those lines. Thanks for the > > feedback! > > This patch is okay with the documentation clarification requested by Joseph. > > I also would suggest removing "but may be enabled in the future" from > the "le" option and limit the comment to ignored on big-endian > targets. > > Also, please add a comment to -maltivec that it defaults to the native > endian order. And for -maltivec=be, please state that this is the > default for big-endian; for -maltivec=le, please state that this is > the default for little-endian. It's important to be clear and > redundant in this type of documentation. > > Thanks, David > Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 206442) +++ gcc/doc/invoke.texi (working copy) @@ -18855,6 +18855,37 @@ the AltiVec instruction set. You may also need to @option{-mabi=altivec} to adjust the current ABI with AltiVec ABI enhancements. +When -maltivec is used, rather than -maltivec=le or -maltivec=be, the +element order for Altivec intrinsics such as vec_splat, vec_extract, +and vec_insert will match array element order corresponding to the +endianness of the target. That is, element zero identifies the +leftmost element in a vector register when targeting a big-endian +platform, and identifies the rightmost element in a vector register +when targeting a little-endian platform. + +@item -maltivec=be +@opindex maltivec=be +Generate Altivec instructions using big-endian element order, +regardless of whether the target is big- or little-endian. This is +the default when targeting a big-endian platform. + +The element order is used to interpret element numbers in Altivec +intrinsics such as vec_splat, vec_extract, and vec_insert. By +default, these will match array element order corresponding to the +endianness for the target. + +@item -maltivec=le +@opindex maltivec=le +Generate Altivec instructions using little-endian element order, +regardless of whether the target is big- or little-endian. This is +the default when targeting a little-endian platform. This option is +currently ignored when targeting a big-endian platform. + +The element order is used to interpret element numbers in Altivec +intrinsics such as vec_splat, vec_extract, and vec_insert. By +default, these will match array element order corresponding to the +endianness for the target. + @item -mvrsave @itemx -mno-vrsave @opindex mvrsave Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 206442) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -140,6 +140,14 @@ maltivec Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions +maltivec=le +Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save +Generate Altivec instructions using little-endian element order + +maltivec=be +Target Report RejectNegative Var(rs6000_altivec_element_order, 2) +Generate Altivec instructions using big-endian element order + mhard-dfp Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 206442) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -3238,6 +3238,18 @@ rs6000_option_override_internal (bool global_init_ && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; + /* -maltivec={le,be} implies -maltivec. */ + if (rs6000_altivec_element_order != 0) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; + + /* Disallow -maltivec=le in big endian mode for now. This is not + known to be useful for anyone. */ + if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1) + { + warning (0, N_("-maltivec=le not allowed for big-endian targets")); + rs6000_altivec_element_order = 0; + } + /* Add some warnings for VSX. */ if (TARGET_VSX) { Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 206442) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -468,6 +468,15 @@ extern int rs6000_vector_align[]; ? rs6000_vector_align[(MODE)] \ : (int)GET_MODE_BITSIZE ((MODE))) +/* Determine the element order to use for vector instructions. By + default we use big-endian element order when targeting big-endian, + and little-endian element order when targeting little-endian. For + programs being ported from BE Power to LE Power, it can sometimes + be useful to use big-endian element order when targeting little-endian. + This is set via -maltivec=be, for example. */ +#define VECTOR_ELT_ORDER_BIG \ + (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) + /* Alignment options for fields in structures for sub-targets following AIX-like ABI. ALIGN_POWER word-aligns FP doubles (default AIX ABI).