From patchwork Fri Oct 11 12:48:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 282734 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 785D52C00CC for ; Fri, 11 Oct 2013 23:48:22 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=vZ5 nZOrpK494gEB/RDjm4G2SrShJhXphiVIzuVRFZzAh1keXLEJrKGB2sxviJnmQ8nm KmiMYLMunb7GhnfqtymSqyKvX0Rkg4xo8/ofh4KbrA9k/atuE3EBNmm9+zw1+ZBr 3IMqkkEy94jsxPNbT0k9RHJYd92wU87zwTW7oLVY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; s=default; bh=3R+n1o89k o9+RF4wCSHAo6ZH59Y=; b=KCCcaQB/XetkoMOXRXDybHmo6wQM00HeNICYeHmpM Z9IMppzcQ+He5KKsv4oOIHysRvEfTtkCk7bg1bZuBX1cePwoAMN8f4l1TAbV62nj QvLUv2d4ABCvdQQDYLEG5+OOxtj26w7DCY2mhLMSVaTsaiwT5DB3LDu2j1AR9FNg uo= Received: (qmail 9092 invoked by alias); 11 Oct 2013 12:48:16 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9083 invoked by uid 89); 11 Oct 2013 12:48:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.1 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e28smtp03.in.ibm.com Received: from e28smtp03.in.ibm.com (HELO e28smtp03.in.ibm.com) (122.248.162.3) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Fri, 11 Oct 2013 12:48:15 +0000 Received: from /spool/local by e28smtp03.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 11 Oct 2013 18:18:08 +0530 Received: from d28relay01.in.ibm.com (d28relay01.in.ibm.com [9.184.220.58]) by d28dlp02.in.ibm.com (Postfix) with ESMTP id 2F1503940058 for ; Fri, 11 Oct 2013 18:17:49 +0530 (IST) Received: from d28av03.in.ibm.com (d28av03.in.ibm.com [9.184.220.65]) by d28relay01.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r9BCohCF27852888 for ; Fri, 11 Oct 2013 18:20:43 +0530 Received: from d28av03.in.ibm.com (localhost [127.0.0.1]) by d28av03.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id r9BCm5Uv013647 for ; Fri, 11 Oct 2013 18:18:05 +0530 Received: from [9.65.233.72] (sig-9-65-233-72.mts.ibm.com [9.65.233.72]) by d28av03.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id r9BCm2Av013431; Fri, 11 Oct 2013 18:18:04 +0530 Message-ID: <1381495700.6275.53.camel@gnopaine> Subject: [PATCH, rs6000] Handle missing permute splits for V2DF/V4SF in little endian From: Bill Schmidt To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com Date: Fri, 11 Oct 2013 07:48:20 -0500 Mime-Version: 1.0 X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13101112-3864-0000-0000-00000A7E5DF0 X-IsSubscribed: yes Hi, In my previous patch to split LE VSX loads and stores to introduce permutes, I managed to miss the vector float modes. This patch corrects the oversight, fixing up a few more test failures. Bootstrapped and tested on both powerpc64-unknown-linux-gnu and powerpc64le-unknown-linux-gnu with no regressions. Ok for trunk? Thanks, Bill 2013-10-11 Bill Schmidt * config/rs6000/vsx.md (*vsx_le_perm_load_v2di): Generalize to handle vector float as well. (*vsx_le_perm_load_v4si): Likewise. (*vsx_le_perm_store_v2di): Likewise. (*vsx_le_perm_store_v4si): Likewise. Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md (revision 203246) +++ gcc/config/rs6000/vsx.md (working copy) @@ -219,18 +219,18 @@ ;; The patterns for LE permuted loads and stores come before the general ;; VSX moves so they match first. -(define_insn_and_split "*vsx_le_perm_load_v2di" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") - (match_operand:V2DI 1 "memory_operand" "Z"))] +(define_insn_and_split "*vsx_le_perm_load_" + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa") + (match_operand:VSX_D 1 "memory_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX" [(set (match_dup 2) - (vec_select:V2DI + (vec_select: (match_dup 1) (parallel [(const_int 1) (const_int 0)]))) (set (match_dup 0) - (vec_select:V2DI + (vec_select: (match_dup 2) (parallel [(const_int 1) (const_int 0)])))] " @@ -242,19 +242,19 @@ [(set_attr "type" "vecload") (set_attr "length" "8")]) -(define_insn_and_split "*vsx_le_perm_load_v4si" - [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa") - (match_operand:V4SI 1 "memory_operand" "Z"))] +(define_insn_and_split "*vsx_le_perm_load_" + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + (match_operand:VSX_W 1 "memory_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX" [(set (match_dup 2) - (vec_select:V4SI + (vec_select: (match_dup 1) (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)]))) (set (match_dup 0) - (vec_select:V4SI + (vec_select: (match_dup 2) (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] @@ -333,18 +333,18 @@ [(set_attr "type" "vecload") (set_attr "length" "8")]) -(define_insn_and_split "*vsx_le_perm_store_v2di" - [(set (match_operand:V2DI 0 "memory_operand" "=Z") - (match_operand:V2DI 1 "vsx_register_operand" "+wa"))] +(define_insn_and_split "*vsx_le_perm_store_" + [(set (match_operand:VSX_D 0 "memory_operand" "=Z") + (match_operand:VSX_D 1 "vsx_register_operand" "+wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX" [(set (match_dup 2) - (vec_select:V2DI + (vec_select: (match_dup 1) (parallel [(const_int 1) (const_int 0)]))) (set (match_dup 0) - (vec_select:V2DI + (vec_select: (match_dup 2) (parallel [(const_int 1) (const_int 0)])))] " @@ -356,19 +356,19 @@ [(set_attr "type" "vecstore") (set_attr "length" "8")]) -(define_insn_and_split "*vsx_le_perm_store_v4si" - [(set (match_operand:V4SI 0 "memory_operand" "=Z") - (match_operand:V4SI 1 "vsx_register_operand" "+wa"))] +(define_insn_and_split "*vsx_le_perm_store_" + [(set (match_operand:VSX_W 0 "memory_operand" "=Z") + (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX" [(set (match_dup 2) - (vec_select:V4SI + (vec_select: (match_dup 1) (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)]))) (set (match_dup 0) - (vec_select:V4SI + (vec_select: (match_dup 2) (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))]