Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	(revision 190546)
+++ gcc/config/sh/sh.md	(working copy)
@@ -541,12 +541,10 @@
 
 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
 ;; and thus we can't put a pop instruction in its delay slot.
-;; ??? On the SH3, the rte instruction does not use the stack, so a pop
+;; On the SH3 and SH4, the rte instruction does not use the stack, so a pop
 ;; instruction can go in the delay slot.
-
 ;; Since a normal return (rts) implicitly uses the PR register,
 ;; we can't allow PR register loads in an rts delay slot.
-
 (define_delay
   (eq_attr "type" "return")
   [(and (eq_attr "in_delay_slot" "yes")
@@ -1154,9 +1152,21 @@
 	(eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
 	       (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
   "TARGET_SH1"
-  "@
-	tst	%S0,%S0\;bf	%,Ldi%=\;tst	%R0,%R0\\n%,Ldi%=:
-	cmp/eq	%S1,%S0\;bf	%,Ldi%=\;cmp/eq	%R1,%R0\\n%,Ldi%=:"
+{
+  static const char* alt[] =
+  {
+       "tst	%S0,%S0"	"\n"
+    "	bf	0f"		"\n"
+    "	tst	%R0,%R0"	"\n"
+    "0:",
+
+       "cmp/eq	%S1,%S0"	"\n"
+    "	bf	0f"		"\n"
+    "	cmp/eq	%R1,%R0"	"\n"
+    "0:"
+  };
+  return alt[which_alternative];
+}
   [(set_attr "length" "6")
    (set_attr "type" "arith3b")])
 
@@ -1189,9 +1199,23 @@
 	(gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
 	       (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
   "TARGET_SH2"
-  "@
-	cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
-	tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
+{
+  static const char* alt[] =
+  {
+       "cmp/eq	%S1,%S0"	"\n"
+    "	bf{.|/}s	0f"	"\n"
+    "	cmp/gt	%S1,%S0"	"\n"
+    "	cmp/hi	%R1,%R0"	"\n"
+    "0:",
+
+        "tst	%S0,%S0"	"\n"
+    "	bf{.|/}s	0f"	"\n"
+    "	cmp/pl	%S0"		"\n"
+    "	cmp/hi	%S0,%R0"	"\n"
+    "0:"
+  };
+  return alt[which_alternative];
+}
   [(set_attr "length" "8")
    (set_attr "type" "arith3")])
 
@@ -1200,9 +1224,19 @@
 	(ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
 	       (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
   "TARGET_SH2"
-  "@
-	cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
-	cmp/pz\\t%S0"
+{
+  static const char* alt[] =
+  {
+       "cmp/eq	%S1,%S0"	"\n"
+    "	bf{.|/}s	0f"	"\n"
+    "	cmp/ge	%S1,%S0"	"\n"
+    "	cmp/hs	%R1,%R0"	"\n"
+    "0:",
+
+       "cmp/pz	%S0"
+  };
+  return alt[which_alternative];
+}
   [(set_attr "length" "8,2")
    (set_attr "type" "arith3,mt_group")])
 
@@ -1215,7 +1249,13 @@
 	(geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
 		(match_operand:DI 1 "arith_reg_operand" "r")))]
   "TARGET_SH2"
-  "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
+{
+  return       "cmp/eq	%S1,%S0"	"\n"
+	 "	bf{.|/}s	0f"	"\n"
+	 "	cmp/hs	%S1,%S0"	"\n"
+	 "	cmp/hs	%R1,%R0"	"\n"
+	 "0:";
+}
   [(set_attr "length" "8")
    (set_attr "type" "arith3")])
 
@@ -1224,7 +1264,13 @@
 	(gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
 		(match_operand:DI 1 "arith_reg_operand" "r")))]
   "TARGET_SH2"
-  "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
+{
+  return       "cmp/eq	%S1,%S0"	"\n"
+	 "	bf{.|/}s	0f"	"\n"
+	 "	cmp/hi	%S1,%S0"	"\n"
+	 "	cmp/hi	%R1,%R0"	"\n"
+	 "0:";
+}
   [(set_attr "length" "8")
    (set_attr "type" "arith3")])
 
@@ -1276,7 +1322,7 @@
   "cmpgtu	%N1, %N2, %0"
   [(set_attr "type" "cmp_media")])
 
-; These two patterns are for combine.
+; This pattern is for combine.
 (define_insn "*cmpne0sisi_media"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
@@ -1527,7 +1573,11 @@
    && (arith_reg_operand (operands[1], SImode)
        || (immediate_operand (operands[1], SImode)
 	   && satisfies_constraint_I08 (operands[1])))"
-  "bt	0f\;mov	%1,%0\\n0:"
+{
+  return       "bt	0f"	"\n"
+	 "	mov	%1,%0"	"\n"
+	 "0:";
+}
   [(set_attr "type" "mt_group,arith") ;; poor approximation
    (set_attr "length" "4")])
 
@@ -1540,7 +1590,11 @@
    && (arith_reg_operand (operands[1], SImode)
        || (immediate_operand (operands[1], SImode)
 	   && satisfies_constraint_I08 (operands[1])))"
-  "bf	0f\;mov	%1,%0\\n0:"
+{
+  return       "bf	0f"	"\n"
+	 "	mov	%1,%0"	"\n"
+	 "0:";
+}
   [(set_attr "type" "mt_group,arith") ;; poor approximation
    (set_attr "length" "4")])
 
@@ -2581,8 +2635,7 @@
 				    (match_operand:DI 2 "register_operand" "r")]
 			 UNSPEC_DIV_INV_TABLE)))]
   "TARGET_SHMEDIA"
-  "@
-	ldx.ub	%1, %2, %0"
+  "ldx.ub	%1, %2, %0"
   [(set_attr "type" "load_media")
    (set_attr "highpart" "user")])
 
@@ -2593,8 +2646,7 @@
 				    (match_operand:DI 2 "register_operand" "r")]
 			 UNSPEC_DIV_INV_TABLE)))]
   "TARGET_SHMEDIA"
-  "@
-	ldx.w	%1, %2, %0"
+  "ldx.w	%1, %2, %0"
   [(set_attr "type" "load_media")
    (set_attr "highpart" "user")])
 
@@ -2924,19 +2976,33 @@
 label:
  sub result, round_scratch, result */
 
-  int likely = TARGET_DIVIDE_INV20L;
-
-  if (! likely) output_asm_insn ("muls.l\t%2, %1 , %8", operands);
-  output_asm_insn ("muls.l\t%2, %3, %0\;xor\t%12, %5, %7", operands);
-  output_asm_insn (likely
-		   ? "bge/l\t%4, %6, %10\;muls.l\t%2, %1 , %8"
-		   : "bge/u\t%4, %6, %10", operands);
-  output_asm_insn ("shari\t%8, 16, %8\;muls.l\t%8, %2, %8", operands);
-  if (! likely) output_asm_insn ("sub\t%0, %7, %0", operands);
-  output_asm_insn ("shari\t%3, 14, %9\;shari\t%8, 30, %8", operands);
-  return (likely
-	  ? "muls.l\t%8, %9, %8\;sub\t%0, %8, %0\n%11:\tadd\t%0, %7, %0"
-	  : "muls.l\t%8, %9, %7\n%11:\tsub\t%0, %7, %0");
+  const bool likely = TARGET_DIVIDE_INV20L;
+  if (likely)
+    return
+	       "muls.l	%2, %3, %0"	"\n"
+	"	xor	%12, %5, %7"	"\n"
+	"	bge/l	%4, %6, %10"	"\n"
+	"	muls.l	%2, %1, %8"	"\n"
+	"	shari	%8, 16, %8"	"\n"
+	"	muls.l	%8, %2, %8"	"\n"
+	"	shari	%3, 14, %9"	"\n"
+	"	shari	%8, 30, %8"	"\n"
+	"	muls.l	%8, %9, %8"	"\n"
+	"	sub	%0, %8, %0"	"\n"
+	"%11:	add	%0, %7, %0";
+  else
+    return
+	       "muls.l	%2, %1, %8"	"\n"
+	"	muls.l	%2, %3, %0"	"\n"
+	"	xor	%12, %5, %7"	"\n"
+	"	bge/u	%4, %6, %10"	"\n"
+	"	shari	%8, 16, %8"	"\n"
+	"	muls.l	%8, %2, %8"	"\n"
+	"	sub	%0, %7, %0"	"\n"
+	"	shari	%3, 14, %9"	"\n"
+	"	shari	%8, 30, %8"	"\n"
+	"	muls.l	%8, %9, %7"	"\n"
+	"%11:	sub	%0, %7, %0";
 })
 
 (define_insn_and_split "divsi_inv_fp"
@@ -3481,7 +3547,7 @@
 	(and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
 		(match_operand:SI 2 "const_int_operand" "Psz")))]
   "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
-  "bclr\\t%W2,%0"
+  "bclr	%W2,%0"
   [(set_attr "type" "arith")])
 
 (define_insn_and_split "anddi3"
@@ -3552,7 +3618,7 @@
 	(ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
 	(match_operand:SI 2 "const_int_operand" "Pso")))]
   "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
-  "bset\\t%V2,%0"
+  "bset	%V2,%0"
   [(set_attr "type" "arith")])
 
 (define_insn "iordi3"
@@ -3672,7 +3738,10 @@
 	(rotate:DI (match_operand:DI 1 "arith_reg_operand" "")
 		   (match_operand:HI 2 "mextr_bit_offset" "")))]
   "TARGET_SHMEDIA"
-  "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
+{
+  if (! mextr_bit_offset (operands[2], HImode))
+    FAIL;
+})
 
 (define_insn "rotldi3_mextr"
   [(set (match_operand:DI 0 "arith_reg_dest" "=r")
@@ -3681,8 +3750,7 @@
   "TARGET_SHMEDIA"
 {
   static char templ[16];
-
-  sprintf (templ, "mextr%d\\t%%1,%%1,%%0",
+  sprintf (templ, "mextr%d	%%1,%%1,%%0",
 	   8 - (int) (INTVAL (operands[2]) >> 3));
   return templ;
 }
@@ -3705,8 +3773,7 @@
   "TARGET_SHMEDIA"
 {
   static char templ[16];
-
-  sprintf (templ, "mextr%d\\t%%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3);
+  sprintf (templ, "mextr%d	%%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3);
   return templ;
 }
   [(set_attr "type" "arith_media")])
@@ -4900,9 +4967,19 @@
 	 (match_operand:SI 1 "arith_reg_operand" "0,0")
 	 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
   "TARGET_SH1 && TARGET_ZDCBRANCH"
-  "@
-	bt\\t0f\;neg\\t%2,%0\\n0:
-	bf\\t0f\;neg\\t%2,%0\\n0:"
+{
+  static const char* alt[] =
+  {
+       "bt	0f"	"\n"
+    "	neg	%2,%0"	"\n"
+    "0:",
+
+       "bf	0f"	"\n"
+    "	neg	%2,%0"	"\n"
+    "0:"
+  };
+  return alt[which_alternative];
+}
   "TARGET_SH1 && ! TARGET_ZDCBRANCH"
   [(const_int 0)]
 {
@@ -5573,9 +5650,16 @@
   [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
 	(truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
   "TARGET_SHMEDIA"
-  "@
-	shlli\\t%1,48,%0\;shlri\\t%0,48,%0
-	st%M0.w	%m0, %1"
+{
+  static const char* alt[] =
+  {
+       "shlli	%1,48,%0"	"\n"
+    "	shlri	%0,48,%0",
+
+       "st%M0.w	%m0, %1"
+  };
+  return alt[which_alternative];
+}
   [(set_attr "type"   "arith_media,store_media")
    (set_attr "length" "8,4")
    (set (attr "highpart")
@@ -5865,9 +5949,9 @@
   "(TARGET_SH1 || TARGET_SH2E || TARGET_SH2A)
    && ! TARGET_SH3"
   "@
-   mov.l   %1,%0
-   lds.l   %1,%0
-   lds.l   %1,%0"
+	mov.l	%1,%0
+	lds.l	%1,%0
+	lds.l	%1,%0"
   [(set_attr "type" "load_si,mem_mac,pload")
    (set_attr "length" "2,2,2")
    (set_attr "in_delay_slot" "no,no,no")])
@@ -6169,7 +6253,12 @@
 		     UNSPEC_ICACHE)
    (clobber (match_scratch:SI 2 "=&r"))]
   "TARGET_HARD_SH4"
-  "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
+{
+  return       "ocbwb	@%0"	"\n"
+	 "	extu.w	%0,%2"	"\n"
+	 "	or	%1,%2"	"\n"
+	 "	mov.l	%0,@%2";
+}
   [(set_attr "length" "8")
    (set_attr "type" "cwb")])
 
@@ -6177,8 +6266,12 @@
   [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
 		    UNSPEC_ICACHE)]
   "TARGET_SH4A_ARCH || TARGET_SH4_300"
-  "ocbwb\\t@%0\;synco\;icbi\\t@%0"
-  [(set_attr "length" "16")
+{
+  return       "ocbwb	@%0"	"\n"
+	 "	synco"		"\n"
+	 "	icbi	@%0";
+}
+  [(set_attr "length" "16")	;; FIXME: Why 16 and not 6?  Looks like typo.
    (set_attr "type" "cwb")])
 
 ;; ??? could make arg 0 an offsettable memory operand to allow to save
@@ -6187,7 +6280,12 @@
   [(unspec_volatile [(match_operand 0 "any_register_operand" "r")]
 		    UNSPEC_ICACHE)]
   "TARGET_SHMEDIA"
-  "ocbwb	%0,0\;synco\;icbi	%0, 0\;synci"
+{
+  return       "ocbwb	%0,0"	"\n"
+	 "	synco"		"\n"
+	 "	icbi	%0,0"	"\n"
+	 "	synci";
+}
   [(set_attr "length" "16")
    (set_attr "type" "invalidate_line_media")])
 
@@ -6911,9 +7009,11 @@
       if (TARGET_FMOVD)
 	return "fmov	%1,%0";
       else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
-	return "fmov	%R1,%R0\n\tfmov	%S1,%S0";
+	return         "fmov	%R1,%R0"	"\n"
+	       "	fmov	%S1,%S0";
       else
-	return "fmov	%S1,%S0\n\tfmov	%R1,%R0";
+	return         "fmov	%S1,%S0"	"\n"
+	       "	fmov	%R1,%R0";
     case 3:
     case 4:
       return "fmov.d	%1,%0";
@@ -8176,9 +8276,9 @@
   "TARGET_SH1"
 {
   if (TARGET_SH2A && (dbr_sequence_length () == 0))
-    return "jsr/n\\t@%0";
+    return "jsr/n	@%0";
   else
-    return "jsr\\t@%0%#";
+    return "jsr	@%0%#";
 }
   [(set_attr "type" "call")
    (set (attr "fp_mode")
@@ -8202,7 +8302,7 @@
   vect_num = sh2a_get_function_vector_number (operands[0]);
   operands[2] = GEN_INT (vect_num * 4);
 
-  return "jsr/n\\t@@(%O2,tbr)";
+  return "jsr/n	@@(%O2,tbr)";
 }
   [(set_attr "type" "call")
    (set (attr "fp_mode")
@@ -8221,7 +8321,10 @@
    (use (match_operand 2 "" ""))
    (clobber (reg:SI PR_REG))]
   "TARGET_SH2"
-  "bsrf	%0\\n%O2:%#"
+{
+  return       "bsrf	%0"	"\n"
+	 "%O2:%#";
+}
   [(set_attr "type" "call")
    (set (attr "fp_mode")
 	(if_then_else (eq_attr "fpu_single" "yes")
@@ -8307,9 +8410,9 @@
   "TARGET_SH1"
 {
   if (TARGET_SH2A && (dbr_sequence_length () == 0))
-    return "jsr/n\\t@%1";
+    return "jsr/n	@%1";
   else
-    return "jsr\\t@%1%#";
+    return "jsr	@%1%#";
 }
   [(set_attr "type" "call")
    (set (attr "fp_mode")
@@ -8334,7 +8437,7 @@
   vect_num = sh2a_get_function_vector_number (operands[1]);
   operands[3] = GEN_INT (vect_num * 4);
 
-  return "jsr/n\\t@@(%O3,tbr)";
+  return "jsr/n	@@(%O3,tbr)";
 }
   [(set_attr "type" "call")
    (set (attr "fp_mode")
@@ -8352,7 +8455,10 @@
    (use (match_operand 3 "" ""))
    (clobber (reg:SI PR_REG))]
   "TARGET_SH2"
-  "bsrf	%1\\n%O3:%#"
+{
+  return       "bsrf	%1"	"\n"
+	 "%O3:%#";
+}
   [(set_attr "type" "call")
    (set (attr "fp_mode")
 	(if_then_else (eq_attr "fpu_single" "yes")
@@ -8738,7 +8844,10 @@
    (use (reg:PSI FPSCR_REG))
    (return)]
   "TARGET_SH2"
-  "braf	%0\\n%O2:%#"
+{
+  return       "braf	%0"	"\n"
+	 "%O2:%#";
+}
   [(set_attr "needs_delay_slot" "yes")
    (set (attr "fp_mode")
 	(if_then_else (eq_attr "fpu_single" "yes")
@@ -8798,9 +8907,16 @@
    ;; because sibcall_epilogue may clobber MACL_REG.
    (clobber (reg:SI MACL_REG))]
   "TARGET_SHCOMPACT"
-  "@
-	jmp	@%0%#
-	jmp	@%0\\n	sts	%2, r0"
+{
+  static const char* alt[] =
+  {
+       "jmp	@%0%#",
+
+       "jmp	@%0"	"\n"
+    "	sts	%2,r0"
+  };
+  return alt[which_alternative];
+}
   [(set_attr "needs_delay_slot" "yes,no")
    (set_attr "length" "2,4")
    (set (attr "fp_mode") (const_string "single"))
@@ -8935,7 +9051,10 @@
    (use (reg:PSI FPSCR_REG))
    (return)]
   "TARGET_SH2"
-  "braf	%1\\n%O3:%#"
+{
+  return       "braf	%1"	"\n"
+	 "%O3:%#";
+}
   [(set_attr "needs_delay_slot" "yes")
    (set (attr "fp_mode")
 	(if_then_else (eq_attr "fpu_single" "yes")
@@ -8983,9 +9102,16 @@
    ;; because sibcall_epilogue may clobber MACL_REG.
    (clobber (reg:SI MACL_REG))]
   "TARGET_SHCOMPACT"
-  "@
-	jmp	@%1%#
-	jmp	@%1\\n	sts	%3, r0"
+{
+  static const char* alt[] =
+  {
+       "jmp	@%1%#",
+
+       "jmp	@%1"	"\n"
+    "	sts	%3,r0"
+  };
+  return alt[which_alternative];
+}
   [(set_attr "needs_delay_slot" "yes,no")
    (set_attr "length" "2,4")
    (set (attr "fp_mode") (const_string "single"))
@@ -9909,13 +10035,18 @@
   switch (GET_MODE (diff_vec))
     {
     case SImode:
-      return "shll2	%1\;mov.l	@(r0,%1),%0";
+      return   "shll2	%1"	"\n"
+	     "	mov.l	@(r0,%1),%0";
     case HImode:
-      return "add	%1,%1\;mov.w	@(r0,%1),%0";
+      return   "add	%1,%1"	"\n"
+	     "	mov.w	@(r0,%1),%0";
     case QImode:
       if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
-	return "mov.b	@(r0,%1),%0\;extu.b	%0,%0";
-      return "mov.b	@(r0,%1),%0";
+	return         "mov.b	@(r0,%1),%0"	"\n"
+	       "	extu.b	%0,%0";
+      else
+	return "mov.b	@(r0,%1),%0";
+
     default:
       gcc_unreachable ();
     }
@@ -9932,29 +10063,33 @@
   "TARGET_SH2 && reload_completed && flag_pic"
 {
   rtx diff_vec = PATTERN (next_real_insn (operands[2]));
-  const char *load;
-
   gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
 
   switch (GET_MODE (diff_vec))
     {
     case SImode:
-      output_asm_insn ("shll2    %1", operands);
-      load = "mov.l	@(r0,%1),%0"; break;
+      return   "shll2	%1"		"\n"
+	     "	add	r0,%1"		"\n"
+	     "	mova	%O3,r0"		"\n"
+	     "  mov.l	@(r0,%1),%0";
     case HImode:
-      output_asm_insn ("add	%1,%1", operands);
-      load = "mov.w	@(r0,%1),%0"; break;
+      return   "add	%1,%1"		"\n"
+	     "	add	r0,%1"		"\n"
+	     "	mova	%O3,r0"		"\n"
+	     "	mov.w	@(r0,%1),%0";
     case QImode:
       if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
-	load = "mov.b	@(r0,%1),%0\;extu.b	%0,%0";
+	return	       "add	r0,%1"		"\n"
+		"	mova	%O3,r0"		"\n"
+		"	mov.b	@(r0,%1),%0"	"\n"
+		"	extu.b	%0,%0";
       else
-	load = "mov.b	@(r0,%1),%0";
-      break;
+	return	       "add	r0,%1"		"\n"
+		"	mova	%O3,r0"		"\n"
+		"	mov.b	@(r0,%1),%0";
     default:
       gcc_unreachable ();
     }
-  output_asm_insn ("add\tr0,%1\;mova\t%O3,r0\\n", operands);
-  return load;
 }
   [(set_attr "length" "8")])
 
@@ -10238,7 +10373,7 @@
    (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
    (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
   "TARGET_SH2A && REGNO (operands[0]) == 15"
-  "movml.l\tr7,@-r15"
+  "movml.l	r7,@-r15"
   [(set_attr "in_delay_slot" "no")])
 
 (define_insn "movml_pop_banked"
@@ -10253,7 +10388,7 @@
    (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
    (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
   "TARGET_SH2A && REGNO (operands[0]) == 15"
-  "movml.l\t@r15+,r7"
+  "movml.l	@r15+,r7"
   [(set_attr "in_delay_slot" "no")])
 
 ;; ------------------------------------------------------------------------
@@ -12171,8 +12306,8 @@
 	    (match_dup 0)))]
   "TARGET_SH2A && TARGET_BITOPS"
   "@
-	bclr.b\\t%1,%0
-	bclr.b\\t%1,@(0,%t0)"
+	bclr.b	%1,%0
+	bclr.b	%1,@(0,%t0)"
 [(set_attr "length" "4,4")])
 
 (define_insn "bclrmem_m2a"
@@ -12181,8 +12316,8 @@
                 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
   "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
   "@
-        bclr.b\\t%W1,%0
-        bclr.b\\t%W1,@(0,%t0)"
+        bclr.b	%W1,%0
+        bclr.b	%W1,@(0,%t0)"
   [(set_attr "length" "4,4")])
 
 ;; Set a bit in a memory location.
@@ -12194,8 +12329,8 @@
 	    (match_dup 0)))]
   "TARGET_SH2A && TARGET_BITOPS"
   "@
-	bset.b\\t%1,%0
-	bset.b\\t%1,@(0,%t0)"
+	bset.b	%1,%0
+	bset.b	%1,@(0,%t0)"
   [(set_attr "length" "4,4")])
 
 (define_insn "bsetmem_m2a"
@@ -12204,8 +12339,8 @@
 		(match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
   "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
   "@
-        bset.b\\t%V1,%0
-        bset.b\\t%V1,@(0,%t0)"
+        bset.b	%V1,%0
+        bset.b	%V1,@(0,%t0)"
   [(set_attr "length" "4,4")])
 
 ;;; Transfer the contents of the T bit to a specified bit of memory.
@@ -12221,8 +12356,8 @@
 		(match_dup 0))))]
   "TARGET_SH2A && TARGET_BITOPS"
   "@
-	bst.b\\t%1,%0
-	bst.b\\t%1,@(0,%t0)"
+	bst.b	%1,%0
+	bst.b	%1,@(0,%t0)"
   [(set_attr "length" "4")])
 
 ;; Store a specified bit of memory in the T bit.
@@ -12234,8 +12369,8 @@
 	    (match_operand 1 "const_int_operand" "K03,K03")))]
   "TARGET_SH2A && TARGET_BITOPS"
   "@
-	bld.b\\t%1,%0
-	bld.b\\t%1,@(0,%t0)"
+	bld.b	%1,%0
+	bld.b	%1,@(0,%t0)"
   [(set_attr "length" "4,4")])
 
 ;; Store a specified bit of memory in the T bit.
@@ -12247,8 +12382,8 @@
 	    (match_operand 1 "const_int_operand" "K03,K03")))]
   "TARGET_SH2A && TARGET_BITOPS"
   "@
-	bld.b\\t%1,%0
-	bld.b\\t%1,@(0,%t0)"
+	bld.b	%1,%0
+	bld.b	%1,@(0,%t0)"
   [(set_attr "length" "4,4")])
 
 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
@@ -12258,7 +12393,7 @@
 			 (const_int 1)
 			 (match_operand 1 "const_int_operand" "K03")))]
   "TARGET_SH2A"
-  "bld\\t%1,%0")
+  "bld	%1,%0")
 
 (define_insn "*bld_regqi"
   [(set (reg:SI T_REG)
@@ -12266,7 +12401,7 @@
 			 (const_int 1)
 			 (match_operand 1 "const_int_operand" "K03")))]
   "TARGET_SH2A"
-  "bld\\t%1,%0")
+  "bld	%1,%0")
 
 ;; Take logical and of a specified bit of memory with the T bit and
 ;; store its result in the T bit.
@@ -12279,8 +12414,8 @@
 		    (match_operand 1 "const_int_operand" "K03,K03"))))]
   "TARGET_SH2A && TARGET_BITOPS"
   "@
-	band.b\\t%1,%0
-	band.b\\t%1,@(0,%t0)"
+	band.b	%1,%0
+	band.b	%1,@(0,%t0)"
   [(set_attr "length" "4,4")])
 
 (define_insn "bandreg_m2a"
@@ -12291,9 +12426,17 @@
 		    (match_operand 2 "const_int_operand" "K03,K03"))
         	(match_operand:SI 3 "register_operand" "r,r")))]
   "TARGET_SH2A && TARGET_BITOPS"
-  "@
-	band.b\\t%2,%1\;movt\\t%0
-	band.b\\t%2,@(0,%t1)\;movt\\t%0"
+{
+  static const char* alt[] =
+  {
+       "band.b	%2,%1"		"\n"
+    "	movt	%0",
+
+       "band.b	%2,@(0,%t1)"	"\n"
+    "	movt	%0"
+  };
+  return alt[which_alternative];
+}
   [(set_attr "length" "6,6")])
 
 ;; Take logical or of a specified bit of memory with the T bit and
@@ -12307,8 +12450,8 @@
 		    (match_operand 1 "const_int_operand" "K03,K03"))))]
   "TARGET_SH2A && TARGET_BITOPS"
   "@
-	bor.b\\t%1,%0
-	bor.b\\t%1,@(0,%t0)"
+	bor.b	%1,%0
+	bor.b	%1,@(0,%t0)"
   [(set_attr "length" "4,4")])
 
 (define_insn "borreg_m2a"
@@ -12319,9 +12462,17 @@
 		    (match_operand 2 "const_int_operand" "K03,K03"))
 		(match_operand:SI 3 "register_operand" "=r,r")))]
   "TARGET_SH2A && TARGET_BITOPS"
-  "@
-	bor.b\\t%2,%1\;movt\\t%0
-	bor.b\\t%2,@(0,%t1)\;movt\\t%0"
+{
+  static const char* alt[] =
+  {
+       "bor.b	%2,%1"		"\n"
+    "	movt	%0",
+
+       "bor.b	%2,@(0,%t1)"	"\n"
+    "	movt	%0"
+  };
+  return alt[which_alternative];
+}
   [(set_attr "length" "6,6")])
 
 ;; Take exclusive or of a specified bit of memory with the T bit and
@@ -12335,8 +12486,8 @@
 		    (match_operand 1 "const_int_operand" "K03,K03"))))]
   "TARGET_SH2A && TARGET_BITOPS"
   "@
-	bxor.b\\t%1,%0
-	bxor.b\\t%1,@(0,%t0)"
+	bxor.b	%1,%0
+	bxor.b	%1,@(0,%t0)"
   [(set_attr "length" "4,4")])
 
 (define_insn "bxorreg_m2a"
@@ -12347,9 +12498,17 @@
 		    (match_operand 2 "const_int_operand" "K03,K03"))
 		(match_operand:SI 3 "register_operand" "=r,r")))]
   "TARGET_SH2A && TARGET_BITOPS"
-  "@
-	bxor.b\\t%2,%1\;movt\\t%0
-	bxor.b\\t%2,@(0,%t1)\;movt\\t%0"
+{
+  static const char* alt[] =
+  {
+       "bxor.b	%2,%1"		"\n"
+    "	movt	%0",
+
+       "bxor.b	%2,@(0,%t1)"	"\n"
+    "	movt	%0"
+  };
+  return alt[which_alternative];
+}
   [(set_attr "length" "6,6")])
 
 
@@ -12584,23 +12743,28 @@
    && reg_unused_after (operands[0], insn)"
   "fmov{.s|}	@(%0,%1),%2")
 
-;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).  */
+;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
 (define_insn "sp_switch_1"
   [(const_int 1) (match_operand:SI 0 "symbol_ref_operand" "s")]
   "TARGET_SH1"
 {
-  output_asm_insn ("mov.l r0,@-r15\;mov.l %0,r0", operands);
-  output_asm_insn ("mov.l @r0,r0\;mov.l r15,@-r0", operands);
-  return "mov r0,r15";
+  return       "mov.l	r0,@-r15"	"\n"
+	 "	mov.l	%0,r0"		"\n"
+	 "	mov.l	@r0,r0"		"\n"
+	 "	mov.l	r15,@-r0"	"\n"
+	 "	mov	r0,r15";
 }
   [(set_attr "length" "10")])
 
 ;; Switch back to the original stack for interrupt functions with the
-;; sp_switch attribute.  */
+;; sp_switch attribute.
 (define_insn "sp_switch_2"
   [(const_int 2)]
   "TARGET_SH1"
-  "mov.l @r15+,r15\;mov.l @r15+,r0"
+{
+  return       "mov.l	@r15+,r15"	"\n"
+	 "	mov.l	@r15+,r0";
+}
   [(set_attr "length" "4")])
 
 ;; Integer vector moves
@@ -12957,7 +13121,8 @@
   "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
 {
   static char templ[21];
-  sprintf (templ, "mextr%d\\t%%N1, %%N2, %%0", (int) INTVAL (operands[3]) >> 3);
+  sprintf (templ, "mextr%d	%%N1, %%N2, %%0",
+	   (int) INTVAL (operands[3]) >> 3);
   return templ;
 }
   [(set_attr "type" "arith_media")])
@@ -12971,7 +13136,8 @@
   "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
 {
   static char templ[21];
-  sprintf (templ, "mextr%d\\t%%N2, %%N1, %%0", (int) INTVAL (operands[4]) >> 3);
+  sprintf (templ, "mextr%d	%%N2, %%N1, %%0",
+	   (int) INTVAL (operands[4]) >> 3);
   return templ;
 }
   [(set_attr "type" "arith_media")])
@@ -14482,7 +14648,11 @@
         (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
    (set (match_scratch:SI 2 "=&r") (const_int 0))]
   "!TARGET_SHMEDIA"
-  "mov.l\t%1, %2\;mov.l\t%2, %0\;mov\t#0, %2"
+{
+  return       "mov.l	%1,%2"	"\n"
+	 "	mov.l	%2,%0"	"\n"
+	 "	mov	#0,%2";
+}
   [(set_attr "type" "other")
    (set_attr "length" "6")])
 
@@ -14491,7 +14661,11 @@
         (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
    (set (match_scratch:SI 2 "=&r") (const_int 0))]
   "TARGET_SHMEDIA"
-  "ld%M1.l\t%m1, %2\;st%M0.l\t%m0, %2\;movi\t0, %2"
+{
+  return       "ld%M1.l	%m1,%2"	"\n"
+	 "	st%M0.l	%m0,%2"	"\n"
+	 "	movi	0,%2";
+}
   [(set_attr "type" "other")
    (set_attr "length" "12")])
 
@@ -14500,7 +14674,11 @@
         (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
    (set (match_scratch:DI 2 "=&r") (const_int 0))]
   "TARGET_SHMEDIA64"
-  "ld%M1.q\t%m1, %2\;st%M0.q\t%m0, %2\;movi\t0, %2"
+{
+  return       "ld%M1.q	%m1,%2"	"\n"
+	 "	st%M0.q	%m0,%2"	"\n"
+	 "	movi	0,%2";
+}
   [(set_attr "type" "other")
    (set_attr "length" "12")])
 
@@ -14546,7 +14724,13 @@
   (set (match_scratch:SI 2 "=&r") (const_int 0))
   (set (match_scratch:SI 3 "=&r") (const_int 0))]
   "!TARGET_SHMEDIA"
-  "mov.l\t%0, %2\;mov.l\t%1, %3\;cmp/eq\t%2, %3\;mov\t#0, %2\;mov\t#0, %3"
+{
+  return       "mov.l	%0,%2"	"\n"
+	 "	mov.l	%1,%3"	"\n"
+	 "	cmp/eq	%2,%3"	"\n"
+	 "	mov	#0,%2"	"\n"
+	 "	mov	#0,%3";
+}
   [(set_attr "type" "other")
    (set_attr "length" "10")])
 
@@ -14557,7 +14741,12 @@
 		   UNSPEC_SP_TEST))
   (set (match_scratch:SI 3 "=&r") (const_int 0))]
   "TARGET_SHMEDIA"
-  "ld%M1.l\t%m1, %0\;ld%M2.l\t%m2, %3\;cmpeq\t%0, %3, %0\;movi\t0, %3"
+{
+  return       "ld%M1.l	%m1,%0"		"\n"
+	 "	ld%M2.l	%m2,%3"		"\n"
+	 "	cmpeq	%0,%3,%0"	"\n"
+	 "	movi	0,%3";
+}
   [(set_attr "type" "other")
    (set_attr "length" "16")])
 
@@ -14568,7 +14757,12 @@
 		   UNSPEC_SP_TEST))
   (set (match_scratch:DI 3 "=&r") (const_int 0))]
   "TARGET_SHMEDIA64"
-  "ld%M1.q\t%m1, %0\;ld%M2.q\t%m2, %3\;cmpeq\t%0, %3, %0\;movi\t0, %3"
+{
+  return       "ld%M1.q	%m1,%0"		"\n"
+	 "	ld%M2.q	%m2,%3"		"\n"
+	 "	cmpeq	%0,%3,%0"	"\n"
+	 "	movi	0,%3";
+}
   [(set_attr "type" "other")
    (set_attr "length" "16")])
 
