From patchwork Fri Aug 10 02:31:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id F26452C0083 for ; Fri, 10 Aug 2012 12:32:42 +1000 (EST) Comment: DKIM? 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Then, now that *insv_z10 is no longer dependent on mode, let gas do some arithmetic, rather than doing it in C and generating new rtl. --- gcc/config/s390/s390.md | 45 ++++++++++++++++----------------------------- 1 files changed, 16 insertions(+), 29 deletions(-) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 76ec9c4..2677fb2 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -3364,27 +3364,15 @@ FAIL; }) -(define_insn "*insv_z10" - [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") - (match_operand 1 "const_int_operand" "I") - (match_operand 2 "const_int_operand" "I")) - (match_operand:GPR 3 "nonimmediate_operand" "d")) +(define_insn "*insv_z10" + [(set (zero_extract:DI + (match_operand:DI 0 "nonimmediate_operand" "+d") + (match_operand 1 "const_int_operand" "") + (match_operand 2 "const_int_operand" "")) + (match_operand:DI 3 "nonimmediate_operand" "d")) (clobber (reg:CC CC_REGNUM))] - "TARGET_Z10 - && (INTVAL (operands[1]) + INTVAL (operands[2])) <= - GET_MODE_BITSIZE (mode)" -{ - int start = INTVAL (operands[2]); - int size = INTVAL (operands[1]); - int offset = 64 - GET_MODE_BITSIZE (mode); - - operands[2] = GEN_INT (offset + start); /* start bit position */ - operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ - operands[4] = GEN_INT (GET_MODE_BITSIZE (mode) - - start - size); /* left shift count */ - - return "risbg\t%0,%3,%b2,%b1,%b4"; -} + "TARGET_Z10" + "risbg\t%0,%3,%2,%2+%1-1,64-%2-%1" [(set_attr "op_type" "RIE") (set_attr "z10prop" "z10_super_E1")]) @@ -3483,15 +3471,14 @@ [(set_attr "op_type" "RIL") (set_attr "z10prop" "z10_fwd_E1")]) -; Update the right-most 32 bit of a DI, or the whole of a SI. -(define_insn "*insv_l_reg_extimm" - [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") - (const_int 32) - (match_operand 1 "const_int_operand" "n")) - (match_operand:P 2 "const_int_operand" "n"))] - "TARGET_EXTIMM - && BITS_PER_WORD - INTVAL (operands[1]) == 32" - "iilf\t%0,%o2" +; Update the right-most 32 bit of a DI. +(define_insn "*insv_l_di_reg_extimm" + [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") + (const_int 32) + (const_int 32)) + (match_operand:DI 1 "const_int_operand" "n"))] + "TARGET_EXTIMM" + "iilf\t%0,%o1" [(set_attr "op_type" "RIL") (set_attr "z10prop" "z10_fwd_A1")])