From patchwork Fri Nov 18 19:11:46 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 126479 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id B74BDB7238 for ; Sat, 19 Nov 2011 06:14:09 +1100 (EST) Received: (qmail 12864 invoked by alias); 18 Nov 2011 19:14:06 -0000 Received: (qmail 12854 invoked by uid 22791); 18 Nov 2011 19:14:05 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-iy0-f175.google.com (HELO mail-iy0-f175.google.com) (209.85.210.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 18 Nov 2011 19:13:19 +0000 Received: by iahk25 with SMTP id k25so4397366iah.20 for ; Fri, 18 Nov 2011 11:13:18 -0800 (PST) Received: by 10.231.5.225 with SMTP id 33mr1001311ibw.3.1321643597080; Fri, 18 Nov 2011 11:13:17 -0800 (PST) Received: from localhost.localdomain (dhcp184-48-96-88.wmr.hon.wayport.net. [184.48.96.88]) by mx.google.com with ESMTPS id l28sm6261662ibc.3.2011.11.18.11.13.15 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 18 Nov 2011 11:13:16 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: mikpe@it.uu.se, schwab@linux-m68k.org Subject: [PATCH 2/2] m68k: Implement CAS and TAS patterns. Date: Fri, 18 Nov 2011 09:11:46 -1000 Message-Id: <1321643506-31962-3-git-send-email-rth@redhat.com> In-Reply-To: <1321643506-31962-1-git-send-email-rth@redhat.com> References: <1321643506-31962-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org --- gcc/config/m68k/m68k.md | 9 +++++ gcc/config/m68k/sync.md | 80 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 0 deletions(-) create mode 100644 gcc/config/m68k/sync.md diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 672ef0d..e4b4b59 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -124,6 +124,10 @@ (define_constants [(UNSPECV_BLOCKAGE 0) + (UNSPECV_CAS_1 1) + (UNSPECV_CAS_2 2) + (UNSPECV_TAS_1 3) + (UNSPECV_TAS_2 4) ]) ;; Registers by name. @@ -255,6 +259,10 @@ (const_int 0)] (const_int 1))) +;; Mode macros for integer operations. +(define_mode_iterator I [QI HI SI]) +(define_mode_attr sz [(QI "%.b") (HI "%.w") (SI "%.l")]) + ;; Mode macros for floating point operations. ;; Valid floating point modes (define_mode_iterator FP [SF DF (XF "TARGET_68881")]) @@ -7806,3 +7814,4 @@ [(set_attr "type" "ib")]) (include "cf.md") +(include "sync.md") diff --git a/gcc/config/m68k/sync.md b/gcc/config/m68k/sync.md new file mode 100644 index 0000000..9a5bcda4 --- /dev/null +++ b/gcc/config/m68k/sync.md @@ -0,0 +1,80 @@ +;; GCC machine description for m68k synchronization instructions. +;; Copyright (C) 2011 +;; Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + + +(define_expand "atomic_compare_and_swap" + [(match_operand:QI 0 "register_operand" "") ;; bool success output + (match_operand:I 1 "register_operand" "") ;; oldval output + (match_operand:I 2 "memory_operand" "") ;; memory + (match_operand:I 3 "register_operand" "") ;; expected input + (match_operand:I 4 "register_operand" "") ;; newval input + (match_operand:SI 5 "const_int_operand" "") ;; is_weak + (match_operand:SI 6 "const_int_operand" "") ;; success model + (match_operand:SI 7 "const_int_operand" "")] ;; failure model + "TARGET_68020 || TARGET_68040" +{ + emit_insn (gen_atomic_compare_and_swap_1 + (operands[0], operands[1], operands[2], + operands[3], operands[4])); + emit_insn (gen_negqi2 (operands[0], operands[0])); + DONE; +}) + +(define_insn "atomic_compare_and_swap_1" + [(set (match_operand:I 1 "register_operand" "=d") + (unspec_volatile:I + [(match_operand:I 2 "memory_operand" "+m") + (match_operand:I 3 "register_operand" "0") + (match_operand:I 4 "register_operand" "d")] + UNSPECV_CAS_1)) + (set (match_dup 2) + (unspec_volatile:I + [(match_dup 2) (match_dup 3) (match_dup 4)] + UNSPECV_CAS_2)) + (set (match_operand:QI 0 "register_operand" "=d") + (unspec_volatile:QI + [(match_dup 2) (match_dup 3) (match_dup 4)] + UNSPECV_CAS_2))] + "TARGET_68020 || TARGET_68040" + ;; Elide the seq if operands[0] is dead. + "cas %1,%4,%2\;seq %0") + +(define_expand "sync_test_and_setqi" + [(match_operand:QI 0 "register_operand" "") + (match_operand:QI 1 "memory_operand" "") + (match_operand:QI 2 "general_operand" "")] + "!(TARGET_68020 || TARGET_68040)" +{ + if (operands[2] != const1_rtx) + FAIL; + emit_insn (gen_sync_test_and_setqi_1 (operands[0], operands[1])); + emit_insn (gen_negqi2 (operands[0], operands[0])); + DONE; +}) + +(define_insn "sync_test_and_setqi_1" + [(set (match_operand:QI 0 "register_operand" "=d") + (unspec_volatile:QI + [(match_operand:QI 1 "memory_operand" "+m")] + UNSPECV_TAS_1)) + (set (match_dup 1) + (unspec_volatile:QI [(match_dup 1)] UNSPECV_TAS_2))] + "!(TARGET_68020 || TARGET_68040)" + "tas %1\;sne %0")