From patchwork Thu Nov 17 20:37:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 126310 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 5B671B7258 for ; Fri, 18 Nov 2011 07:38:29 +1100 (EST) Received: (qmail 22346 invoked by alias); 17 Nov 2011 20:38:20 -0000 Received: (qmail 22260 invoked by uid 22791); 17 Nov 2011 20:38:18 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-iy0-f175.google.com (HELO mail-iy0-f175.google.com) (209.85.210.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 17 Nov 2011 20:38:04 +0000 Received: by iahk25 with SMTP id k25so2904719iah.20 for ; Thu, 17 Nov 2011 12:38:03 -0800 (PST) Received: by 10.42.137.6 with SMTP id w6mr290136ict.5.1321562283362; Thu, 17 Nov 2011 12:38:03 -0800 (PST) Received: from localhost.localdomain (dhcp184-48-96-88.wmr.hon.wayport.net. [184.48.96.88]) by mx.google.com with ESMTPS id eb23sm5755730ibb.2.2011.11.17.12.38.01 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 17 Nov 2011 12:38:02 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: davem@davemloft.net, ebotcazou@libertysurf.fr Subject: [PATCH 4/5] sparc: Convert to atomic_exchange. Date: Thu, 17 Nov 2011 10:37:44 -1000 Message-Id: <1321562265-12743-5-git-send-email-rth@redhat.com> In-Reply-To: <1321562265-12743-1-git-send-email-rth@redhat.com> References: <1321562265-12743-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org --- gcc/config/sparc/sync.md | 91 +++++++++++++++------------------------------- 1 files changed, 30 insertions(+), 61 deletions(-) diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md index d38a828..782aa60 100644 --- a/gcc/config/sparc/sync.md +++ b/gcc/config/sparc/sync.md @@ -19,6 +19,7 @@ ;; . (define_mode_iterator I12MODE [QI HI]) +(define_mode_iterator I124MODE [QI HI SI]) (define_mode_iterator I24MODE [HI SI]) (define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")]) (define_mode_attr modesuffix [(SI "") (DI "x")]) @@ -32,14 +33,6 @@ DONE; }) -(define_expand "memory_barrier" - [(const_int 0)] - "TARGET_V8 || TARGET_V9" -{ - sparc_emit_membar_for_model (MEMMODEL_SEQ_CST, 3, 3); - DONE; -}) - (define_expand "membar" [(set (match_dup 1) (unspec:BLK [(match_dup 1) @@ -198,46 +191,22 @@ [(set_attr "type" "multi") (set_attr "length" "8")]) -;;;;;;;; - -(define_expand "sync_lock_test_and_set" - [(match_operand:I12MODE 0 "register_operand" "") - (match_operand:I12MODE 1 "memory_operand" "") - (match_operand:I12MODE 2 "arith_operand" "")] - "!TARGET_V9" +(define_expand "atomic_exchangesi" + [(match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "memory_operand" "") + (match_operand:SI 2 "register_operand" "") + (match_operand:SI 3 "const_int_operand" "")] + "TARGET_V8 || TARGET_V9" { - if (operands[2] != const1_rtx) - FAIL; - if (TARGET_V8) - emit_insn (gen_memory_barrier ()); - if (mode != QImode) - operands[1] = adjust_address (operands[1], QImode, 0); - emit_insn (gen_ldstub (operands[0], operands[1])); - DONE; -}) + enum memmodel model = (enum memmodel) INTVAL (operands[3]); -(define_expand "sync_lock_test_and_setsi" - [(parallel - [(set (match_operand:SI 0 "register_operand" "") - (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "")] - UNSPECV_SWAP)) - (set (match_dup 1) - (match_operand:SI 2 "arith_operand" ""))])] - "" -{ - if (! TARGET_V8 && ! TARGET_V9) - { - if (operands[2] != const1_rtx) - FAIL; - operands[1] = adjust_address (operands[1], QImode, 0); - emit_insn (gen_ldstubsi (operands[0], operands[1])); - DONE; - } - emit_insn (gen_memory_barrier ()); - operands[2] = force_reg (SImode, operands[2]); + sparc_emit_membar_for_model (model, 3, 1); + emit_insn (gen_swapsi (operands[0], operands[1], operands[2])); + sparc_emit_membar_for_model (model, 3, 2); + DONE; }) -(define_insn "*swapsi" +(define_insn "swapsi" [(set (match_operand:SI 0 "register_operand" "=r") (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")] UNSPECV_SWAP)) @@ -247,24 +216,24 @@ "swap\t%1, %0" [(set_attr "type" "multi")]) -(define_expand "ldstubqi" - [(parallel [(set (match_operand:QI 0 "register_operand" "") - (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "")] - UNSPECV_LDSTUB)) - (set (match_dup 1) (const_int -1))])] - "" - "") - -(define_expand "ldstub" - [(parallel [(set (match_operand:I24MODE 0 "register_operand" "") - (zero_extend:I24MODE - (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "")] - UNSPECV_LDSTUB))) - (set (match_dup 1) (const_int -1))])] +;; The original V7 LDSTUB can only be implemented with sync_test_and_set. +;; The expanders have already tried atomic_exchange for V8, so we do not +;; need to fall back to using SWAP here. +(define_expand "sync_lock_test_and_set" + [(match_operand:I124MODE 0 "register_operand" "") + (match_operand:I124MODE 1 "memory_operand" "") + (match_operand:I124MODE 2 "arith_operand" "")] "" - "") +{ + if (operands[2] != const1_rtx) + FAIL; + if (mode != QImode) + operands[1] = adjust_address (operands[1], QImode, 0); + emit_insn (gen_ldstub (operands[0], operands[1])); + DONE; +}) -(define_insn "*ldstubqi" +(define_insn "ldstubqi" [(set (match_operand:QI 0 "register_operand" "=r") (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")] UNSPECV_LDSTUB)) @@ -273,7 +242,7 @@ "ldstub\t%1, %0" [(set_attr "type" "multi")]) -(define_insn "*ldstub" +(define_insn "ldstub" [(set (match_operand:I24MODE 0 "register_operand" "=r") (zero_extend:I24MODE (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]