From patchwork Tue Oct 25 00:17:28 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 121460 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 840CE1007D7 for ; Tue, 25 Oct 2011 11:18:46 +1100 (EST) Received: (qmail 22801 invoked by alias); 25 Oct 2011 00:18:18 -0000 Received: (qmail 22274 invoked by uid 22791); 25 Oct 2011 00:18:11 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-gx0-f175.google.com (HELO mail-gx0-f175.google.com) (209.85.161.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 25 Oct 2011 00:17:43 +0000 Received: by ggnj1 with SMTP id j1so5523166ggn.20 for ; Mon, 24 Oct 2011 17:17:43 -0700 (PDT) Received: by 10.150.240.15 with SMTP id n15mr22493668ybh.81.1319501863267; Mon, 24 Oct 2011 17:17:43 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net. [71.227.161.214]) by mx.google.com with ESMTPS id z6sm67663882anf.22.2011.10.24.17.17.42 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 24 Oct 2011 17:17:42 -0700 (PDT) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com Subject: [PATCH 5/6] rs6000: Remove some vec_extract_even/odd expanders. Date: Mon, 24 Oct 2011 17:17:28 -0700 Message-Id: <1319501849-12807-6-git-send-email-rth@redhat.com> In-Reply-To: <1319501849-12807-1-git-send-email-rth@redhat.com> References: <1319501849-12807-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org The ones that expand to VPERM can be handled by generic code. The even v4si and v4sf expanders remain until vector.md can be updated to not invoke them directly. --- gcc/config/rs6000/altivec.md | 134 +----------------------------------------- 1 files changed, 2 insertions(+), 132 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 84c5444..a3a8d77 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2429,6 +2429,7 @@ "stvrxl %1,%y0" [(set_attr "type" "vecstore")]) +;; ??? This is still used directly by vector.md (define_expand "vec_extract_evenv4si" [(set (match_operand:V4SI 0 "register_operand" "") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "") @@ -2462,6 +2463,7 @@ DONE; }") +;; ??? This is still used directly by vector.md (define_expand "vec_extract_evenv4sf" [(set (match_operand:V4SF 0 "register_operand" "") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "") @@ -2495,138 +2497,6 @@ DONE; }") -(define_expand "vec_extract_evenv8hi" - [(set (match_operand:V8HI 0 "register_operand" "") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "") - (match_operand:V8HI 2 "register_operand" "")] - UNSPEC_EXTEVEN_V8HI))] - "TARGET_ALTIVEC" - " -{ - rtx mask = gen_reg_rtx (V16QImode); - rtvec v = rtvec_alloc (16); - - RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0); - RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1); - RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4); - RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 5); - RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8); - RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9); - RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12); - RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 13); - RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17); - RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20); - RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 21); - RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24); - RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25); - RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28); - RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 29); - emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); - emit_insn (gen_altivec_vperm_v8hi (operands[0], operands[1], operands[2], mask)); - - DONE; -}") - -(define_expand "vec_extract_evenv16qi" - [(set (match_operand:V16QI 0 "register_operand" "") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "") - (match_operand:V16QI 2 "register_operand" "")] - UNSPEC_EXTEVEN_V16QI))] - "TARGET_ALTIVEC" - " -{ - rtx mask = gen_reg_rtx (V16QImode); - rtvec v = rtvec_alloc (16); - - RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0); - RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 2); - RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4); - RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 6); - RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8); - RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10); - RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12); - RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 14); - RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16); - RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 18); - RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20); - RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 22); - RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24); - RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 26); - RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28); - RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 30); - emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); - emit_insn (gen_altivec_vperm_v16qi (operands[0], operands[1], operands[2], mask)); - - DONE; -}") - -(define_expand "vec_extract_oddv4si" - [(set (match_operand:V4SI 0 "register_operand" "") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "register_operand" "")] - UNSPEC_EXTODD_V4SI))] - "TARGET_ALTIVEC" - " -{ - rtx mask = gen_reg_rtx (V16QImode); - rtvec v = rtvec_alloc (16); - - RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4); - RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5); - RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6); - RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7); - RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12); - RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13); - RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14); - RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15); - RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20); - RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21); - RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22); - RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23); - RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28); - RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29); - RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30); - RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31); - emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); - emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask)); - - DONE; -}") - -(define_expand "vec_extract_oddv4sf" - [(set (match_operand:V4SF 0 "register_operand" "") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "") - (match_operand:V4SF 2 "register_operand" "")] - UNSPEC_EXTODD_V4SF))] - "TARGET_ALTIVEC" - " -{ - rtx mask = gen_reg_rtx (V16QImode); - rtvec v = rtvec_alloc (16); - - RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4); - RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5); - RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6); - RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7); - RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12); - RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13); - RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14); - RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15); - RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20); - RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21); - RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22); - RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23); - RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28); - RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29); - RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30); - RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31); - emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); - emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask)); - - DONE; -}") - (define_insn "vpkuhum_nomode" [(set (match_operand:V16QI 0 "register_operand" "=v") (unspec:V16QI [(match_operand 1 "register_operand" "v")