From patchwork Tue Oct 25 00:17:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 121461 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 8AD821007D7 for ; Tue, 25 Oct 2011 11:18:53 +1100 (EST) Received: (qmail 23094 invoked by alias); 25 Oct 2011 00:18:21 -0000 Received: (qmail 22287 invoked by uid 22791); 25 Oct 2011 00:18:11 -0000 X-SWARE-Spam-Status: No, hits=-1.0 required=5.0 tests=AWL, BAYES_50, DKIM_SIGNED, DKIM_VALID, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-gy0-f175.google.com (HELO mail-gy0-f175.google.com) (209.85.160.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 25 Oct 2011 00:17:43 +0000 Received: by gyc15 with SMTP id 15so7199213gyc.20 for ; Mon, 24 Oct 2011 17:17:42 -0700 (PDT) Received: by 10.236.197.72 with SMTP id s48mr4447332yhn.81.1319501862174; Mon, 24 Oct 2011 17:17:42 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net. [71.227.161.214]) by mx.google.com with ESMTPS id z6sm67663882anf.22.2011.10.24.17.17.41 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 24 Oct 2011 17:17:41 -0700 (PDT) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: uweigand@de.ibm.com Subject: [PATCH 4/6] spu: Remove vec_extract_even/odd and vec_interleave expanders. Date: Mon, 24 Oct 2011 17:17:27 -0700 Message-Id: <1319501849-12807-5-git-send-email-rth@redhat.com> In-Reply-To: <1319501849-12807-1-git-send-email-rth@redhat.com> References: <1319501849-12807-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org --- gcc/config/spu/spu.md | 433 ------------------------------------------------- 1 files changed, 0 insertions(+), 433 deletions(-) diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md index ca2cad9..3178a6d 100644 --- a/gcc/config/spu/spu.md +++ b/gcc/config/spu/spu.md @@ -4947,439 +4947,6 @@ DONE; }) -(define_expand "vec_extract_evenv4si" - [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") - (vec_concat:V4SI - (vec_select:V2SI - (match_operand:V4SI 1 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 2)])) - (vec_select:V2SI - (match_operand:V4SI 2 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 2)]))))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x00, 0x01, 0x02, 0x03, - 0x08, 0x09, 0x0A, 0x0B, - 0x10, 0x11, 0x12, 0x13, - 0x18, 0x19, 0x1A, 0x1B}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - - -(define_expand "vec_extract_evenv4sf" - [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") - (vec_concat:V4SF - (vec_select:V2SF - (match_operand:V4SF 1 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 2)])) - (vec_select:V2SF - (match_operand:V4SF 2 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 2)]))))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x00, 0x01, 0x02, 0x03, - 0x08, 0x09, 0x0A, 0x0B, - 0x10, 0x11, 0x12, 0x13, - 0x18, 0x19, 0x1A, 0x1B}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_extract_evenv8hi" - [(set (match_operand:V8HI 0 "spu_reg_operand" "=r") - (vec_concat:V8HI - (vec_select:V4HI - (match_operand:V8HI 1 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])) - (vec_select:V4HI - (match_operand:V8HI 2 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x00, 0x01, 0x04, 0x05, - 0x08, 0x09, 0x0C, 0x0D, - 0x10, 0x11, 0x14, 0x15, - 0x18, 0x19, 0x1C, 0x1D}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_extract_evenv16qi" - [(set (match_operand:V16QI 0 "spu_reg_operand" "=r") - (vec_concat:V16QI - (vec_select:V8QI - (match_operand:V16QI 1 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6) - (const_int 8)(const_int 10)(const_int 12)(const_int 14)])) - (vec_select:V8QI - (match_operand:V16QI 2 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6) - (const_int 8)(const_int 10)(const_int 12)(const_int 14)]))))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x00, 0x02, 0x04, 0x06, - 0x08, 0x0A, 0x0C, 0x0E, - 0x10, 0x12, 0x14, 0x16, - 0x18, 0x1A, 0x1C, 0x1E}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_extract_oddv4si" - [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") - (vec_concat:V4SI - (vec_select:V2SI - (match_operand:V4SI 1 "spu_reg_operand" "r") - (parallel [(const_int 1)(const_int 3)])) - (vec_select:V2SI - (match_operand:V4SI 2 "spu_reg_operand" "r") - (parallel [(const_int 1)(const_int 3)]))))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x04, 0x05, 0x06, 0x07, - 0x0C, 0x0D, 0x0E, 0x0F, - 0x14, 0x15, 0x16, 0x17, - 0x1C, 0x1D, 0x1E, 0x1F}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_extract_oddv4sf" - [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") - (vec_concat:V4SF - (vec_select:V2SF - (match_operand:V4SF 1 "spu_reg_operand" "r") - (parallel [(const_int 1)(const_int 3)])) - (vec_select:V2SF - (match_operand:V4SF 2 "spu_reg_operand" "r") - (parallel [(const_int 1)(const_int 3)]))))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x04, 0x05, 0x06, 0x07, - 0x0C, 0x0D, 0x0E, 0x0F, - 0x14, 0x15, 0x16, 0x17, - 0x1C, 0x1D, 0x1E, 0x1F}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_extract_oddv8hi" - [(set (match_operand:V8HI 0 "spu_reg_operand" "=r") - (vec_concat:V8HI - (vec_select:V4HI - (match_operand:V8HI 1 "spu_reg_operand" "r") - (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])) - (vec_select:V4HI - (match_operand:V8HI 2 "spu_reg_operand" "r") - (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x02, 0x03, 0x06, 0x07, - 0x0A, 0x0B, 0x0E, 0x0F, - 0x12, 0x13, 0x16, 0x17, - 0x1A, 0x1B, 0x1E, 0x1F}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_extract_oddv16qi" - [(set (match_operand:V16QI 0 "spu_reg_operand" "=r") - (vec_concat:V16QI - (vec_select:V8QI - (match_operand:V16QI 1 "spu_reg_operand" "r") - (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7) - (const_int 9)(const_int 11)(const_int 13)(const_int 15)])) - (vec_select:V8QI - (match_operand:V16QI 2 "spu_reg_operand" "r") - (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7) - (const_int 9)(const_int 11)(const_int 13)(const_int 15)]))))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x01, 0x03, 0x05, 0x07, - 0x09, 0x0B, 0x0D, 0x0F, - 0x11, 0x13, 0x15, 0x17, - 0x19, 0x1B, 0x1D, 0x1F}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_interleave_highv4sf" - [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") - (vec_select:V4SF - (vec_concat:V4SF - (vec_select:V2SF - (match_operand:V4SF 1 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 1)])) - (vec_select:V2SF - (match_operand:V4SF 2 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 1)]))) - (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x00, 0x01, 0x02, 0x03, - 0x10, 0x11, 0x12, 0x13, - 0x04, 0x05, 0x06, 0x07, - 0x14, 0x15, 0x16, 0x17}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_interleave_lowv4sf" - [(set (match_operand:V4SF 0 "spu_reg_operand" "=r") - (vec_select:V4SF - (vec_concat:V4SF - (vec_select:V2SF - (match_operand:V4SF 1 "spu_reg_operand" "r") - (parallel [(const_int 2)(const_int 3)])) - (vec_select:V2SF - (match_operand:V4SF 2 "spu_reg_operand" "r") - (parallel [(const_int 2)(const_int 3)]))) - (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x08, 0x09, 0x0A, 0x0B, - 0x18, 0x19, 0x1A, 0x1B, - 0x0C, 0x0D, 0x0E, 0x0F, - 0x1C, 0x1D, 0x1E, 0x1F}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_interleave_highv4si" - [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") - (vec_select:V4SI - (vec_concat:V4SI - (vec_select:V2SI - (match_operand:V4SI 1 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 1)])) - (vec_select:V2SI - (match_operand:V4SI 2 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 1)]))) - (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x00, 0x01, 0x02, 0x03, - 0x10, 0x11, 0x12, 0x13, - 0x04, 0x05, 0x06, 0x07, - 0x14, 0x15, 0x16, 0x17}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_interleave_lowv4si" - [(set (match_operand:V4SI 0 "spu_reg_operand" "=r") - (vec_select:V4SI - (vec_concat:V4SI - (vec_select:V2SI - (match_operand:V4SI 1 "spu_reg_operand" "r") - (parallel [(const_int 2)(const_int 3)])) - (vec_select:V2SI - (match_operand:V4SI 2 "spu_reg_operand" "r") - (parallel [(const_int 2)(const_int 3)]))) - (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x08, 0x09, 0x0A, 0x0B, - 0x18, 0x19, 0x1A, 0x1B, - 0x0C, 0x0D, 0x0E, 0x0F, - 0x1C, 0x1D, 0x1E, 0x1F}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_interleave_highv8hi" - [(set (match_operand:V8HI 0 "spu_reg_operand" "=r") - (vec_select:V8HI - (vec_concat:V8HI - (vec_select:V4HI - (match_operand:V8HI 1 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)])) - (vec_select:V4HI - (match_operand:V8HI 2 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)]))) - (parallel [(const_int 0)(const_int 4)(const_int 1)(const_int 5) - (const_int 2)(const_int 6)(const_int 3)(const_int 7)])))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x00, 0x01, 0x10, 0x11, - 0x02, 0x03, 0x12, 0x13, - 0x04, 0x05, 0x14, 0x15, - 0x06, 0x07, 0x16, 0x17}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; - }") - -(define_expand "vec_interleave_lowv8hi" - [(set (match_operand:V8HI 0 "spu_reg_operand" "=r") - (vec_select:V8HI - (vec_concat:V8HI - (vec_select:V4HI - (match_operand:V8HI 1 "spu_reg_operand" "r") - (parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)])) - (vec_select:V4HI - (match_operand:V8HI 2 "spu_reg_operand" "r") - (parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)]))) - (parallel [(const_int 0)(const_int 4)(const_int 1)(const_int 5) - (const_int 2)(const_int 6)(const_int 3)(const_int 7)])))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x08, 0x09, 0x18, 0x19, - 0x0A, 0x0B, 0x1A, 0x1B, - 0x0C, 0x0D, 0x1C, 0x1D, - 0x0E, 0x0F, 0x1E, 0x1F}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_interleave_highv16qi" - [(set (match_operand:V16QI 0 "spu_reg_operand" "=r") - (vec_select:V16QI - (vec_concat:V16QI - (vec_select:V8QI - (match_operand:V16QI 1 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3) - (const_int 4)(const_int 5)(const_int 6)(const_int 7)])) - (vec_select:V8QI - (match_operand:V16QI 2 "spu_reg_operand" "r") - (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3) - (const_int 4)(const_int 5)(const_int 6)(const_int 7)]))) - (parallel [(const_int 0)(const_int 8)(const_int 1)(const_int 9) - (const_int 2)(const_int 10)(const_int 3)(const_int 11) - (const_int 4)(const_int 12)(const_int 5)(const_int 13) - (const_int 6)(const_int 14)(const_int 7)(const_int 15)])))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x00, 0x10, 0x01, 0x11, - 0x02, 0x12, 0x03, 0x13, - 0x04, 0x14, 0x05, 0x15, - 0x06, 0x16, 0x07, 0x17}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - -(define_expand "vec_interleave_lowv16qi" - [(set (match_operand:V16QI 0 "spu_reg_operand" "=r") - (vec_select:V16QI - (vec_concat:V16QI - (vec_select:V8QI - (match_operand:V16QI 1 "spu_reg_operand" "r") - (parallel [(const_int 8)(const_int 9)(const_int 10)(const_int 11) - (const_int 12)(const_int 13)(const_int 14)(const_int 15)])) - (vec_select:V8QI - (match_operand:V16QI 2 "spu_reg_operand" "r") - (parallel [(const_int 8)(const_int 9)(const_int 10)(const_int 11) - (const_int 12)(const_int 13)(const_int 14)(const_int 15)]))) - (parallel [(const_int 0)(const_int 8)(const_int 1)(const_int 9) - (const_int 2)(const_int 10)(const_int 3)(const_int 11) - (const_int 4)(const_int 12)(const_int 5)(const_int 13) - (const_int 6)(const_int 14)(const_int 7)(const_int 15)])))] - - "" - " -{ - rtx mask = gen_reg_rtx (TImode); - unsigned char arr[16] = { - 0x08, 0x18, 0x09, 0x19, - 0x0A, 0x1A, 0x0B, 0x1B, - 0x0C, 0x1C, 0x0D, 0x1D, - 0x0E, 0x1E, 0x0F, 0x1F}; - - emit_move_insn (mask, array_to_constant (TImode, arr)); - emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask)); - DONE; -}") - (define_expand "vec_pack_trunc_v8hi" [(set (match_operand:V16QI 0 "spu_reg_operand" "=r") (vec_concat:V16QI