From patchwork Fri Jan 14 16:08:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 78945 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id D6BE5B70D4 for ; Sat, 15 Jan 2011 03:12:12 +1100 (EST) Received: (qmail 27132 invoked by alias); 14 Jan 2011 16:09:56 -0000 Received: (qmail 26993 invoked by uid 22791); 14 Jan 2011 16:09:52 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE X-Spam-Check-By: sourceware.org Received: from a.mail.sonic.net (HELO a.mail.sonic.net) (64.142.16.245) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 14 Jan 2011 16:09:45 +0000 Received: from are.twiddle.net (are.twiddle.net [75.101.38.216]) by a.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p0EG9iB9003858 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 14 Jan 2011 08:09:44 -0800 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (8.14.4/8.14.4) with ESMTP id p0EG9hoE002095; Fri, 14 Jan 2011 08:09:43 -0800 Received: from anchor.twiddle.home (localhost.localdomain [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id p0EG9bZY028717; Fri, 14 Jan 2011 08:09:39 -0800 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id p0EG9ZBO028716; Fri, 14 Jan 2011 08:09:35 -0800 From: rth@redhat.com To: gcc-patches@gcc.gnu.org Cc: nickc@redhat.com, Richard Henderson Subject: [PATCH 12/14] rx: Replace sat builtin with ssaddsi3 pattern. Date: Fri, 14 Jan 2011 08:08:27 -0800 Message-Id: <1295021309-28608-13-git-send-email-rth@redhat.com> In-Reply-To: <1295021309-28608-1-git-send-email-rth@redhat.com> References: <1295021309-28608-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org From: Richard Henderson A standalone __builtin_rx_sat isn't implementable due to needing to keep the flags live before reload. Instead provide a saturating add pattern, which hopefully will be pattern-matched by high-level optimizations. --- gcc/config/rx/rx.c | 4 ---- gcc/config/rx/rx.md | 41 +++++++++++++++++++++++++++++++---------- 2 files changed, 31 insertions(+), 14 deletions(-) diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c index 8cc46e7..0179b1f 100644 --- a/gcc/config/rx/rx.c +++ b/gcc/config/rx/rx.c @@ -1847,7 +1847,6 @@ enum rx_builtin RX_BUILTIN_REVW, RX_BUILTIN_RMPA, RX_BUILTIN_ROUND, - RX_BUILTIN_SAT, RX_BUILTIN_SETPSW, RX_BUILTIN_WAIT, RX_BUILTIN_max @@ -1902,7 +1901,6 @@ rx_init_builtins (void) ADD_RX_BUILTIN1 (RACW, "racw", void, integer); ADD_RX_BUILTIN1 (ROUND, "round", intSI, float); ADD_RX_BUILTIN1 (REVW, "revw", intSI, intSI); - ADD_RX_BUILTIN1 (SAT, "sat", intSI, intSI); ADD_RX_BUILTIN1 (WAIT, "wait", void, void); } @@ -2100,8 +2098,6 @@ rx_expand_builtin (tree exp, case RX_BUILTIN_ROUND: return rx_expand_builtin_round (op, target); case RX_BUILTIN_REVW: return rx_expand_int_builtin_1_arg (op, target, gen_revw, false); - case RX_BUILTIN_SAT: return rx_expand_int_builtin_1_arg - (op, target, gen_sat, false); case RX_BUILTIN_WAIT: emit_insn (gen_wait ()); return NULL_RTX; default: diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md index 7fa8668..a3db92c 100644 --- a/gcc/config/rx/rx.md +++ b/gcc/config/rx/rx.md @@ -1378,6 +1378,37 @@ [(set_attr "length" "3,2,3")] ) +;; Saturate to 32-bits +(define_insn_and_split "ssaddsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (ss_plus:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "rx_source_operand" "riQ"))) + (clobber (reg:CC CC_REG))] + "" + "#" + "reload_completed" + [(parallel [(set (match_dup 0) + (plus:SI (match_dup 1) (match_dup 2))) + (set (reg:CC_ZSC CC_REG) + (compare:CC_ZSC + (plus:SI (match_dup 1) (match_dup 2)) + (const_int 0)))]) + (set (match_dup 0) + (unspec:SI [(match_dup 0) (reg:CC CC_REG)] + UNSPEC_BUILTIN_SAT))] + "" +) + +(define_insn "*sat" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "0") + (reg:CC CC_REG)] + UNSPEC_BUILTIN_SAT))] + "reload_completed" + "sat\t%0" + [(set_attr "length" "2")] +) + (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0") @@ -2068,16 +2099,6 @@ (set_attr "length" "3,5")] ) -;; Saturate to 32-bits -(define_insn "sat" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:SI 1 "register_operand" "0")] - UNSPEC_BUILTIN_SAT))] - "" - "sat\t%0" - [(set_attr "length" "2")] -) - ;;---------- Control Registers ------------------------ ;; Clear Processor Status Word