@@ -216,3 +216,28 @@
(and (match_test "TARGET_H8300SX")
(match_code "mem")
(match_test "CONSTANT_P (XEXP (op, 0))")))
+
+(define_register_constraint "Z0" "NOT_R0_REGS"
+ "@internal")
+
+(define_register_constraint "Z1" "NOT_R1_REGS"
+ "@internal")
+
+(define_register_constraint "Z2" "NOT_R2_REGS"
+ "@internal")
+
+(define_register_constraint "Z3" "NOT_R3_REGS"
+ "@internal")
+
+(define_register_constraint "Z4" "NOT_R4_REGS"
+ "@internal")
+
+(define_register_constraint "Z5" "NOT_R5_REGS"
+ "@internal")
+
+(define_register_constraint "Z6" "NOT_R6_REGS"
+ "@internal")
+
+(define_register_constraint "Z7" "NOT_SP_REGS"
+ "@internal")
+
@@ -282,6 +282,8 @@ extern const char * const *h8_reg_names;
enum reg_class {
NO_REGS, COUNTER_REGS, SOURCE_REGS, DESTINATION_REGS,
+ NOT_R0_REGS, NOT_R1_REGS, NOT_R2_REGS, NOT_R3_REGS,
+ NOT_R4_REGS, NOT_R5_REGS, NOT_R6_REGS, NOT_SP_REGS,
GENERAL_REGS, MAC_REGS, ALL_REGS, LIM_REG_CLASSES
};
@@ -291,6 +293,8 @@ enum reg_class {
#define REG_CLASS_NAMES \
{ "NO_REGS", "COUNTER_REGS", "SOURCE_REGS", "DESTINATION_REGS", \
+ "NOT_R0_REGS", "NOT_R1_REGS", "NOT_R2_REGS", "NOT_R3_REGS", \
+ "NOT_R4_REGS", "NOT_R5_REGS", "NOT_R6_REGS", "NOT_SP_REGS", \
"GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" }
/* Define which registers fit in which classes.
@@ -302,6 +306,14 @@ enum reg_class {
{0x010}, /* COUNTER_REGS */ \
{0x020}, /* SOURCE_REGS */ \
{0x040}, /* DESTINATION_REGS */ \
+ {0x0fe}, /* NOT_R0_REGS */ \
+ {0x0fd}, /* NOT_R1_REGS */ \
+ {0x0fb}, /* NOT_R2_REGS */ \
+ {0x0f7}, /* NOT_R3_REGS */ \
+ {0x0ef}, /* NOT_R4_REGS */ \
+ {0x0df}, /* NOT_R5_REGS */ \
+ {0x0bf}, /* NOT_R6_REGS */ \
+ {0x07f}, /* NOT_SP_REGS */ \
{0xeff}, /* GENERAL_REGS */ \
{0x100}, /* MAC_REGS */ \
{0xfff}, /* ALL_REGS */ \
GCC does not allow a the operand of an autoinc addressing mode to overlap with another soure operand in the same insn. This is primarly enforced with insn conditions. However, cases can slip through LRA and reload. To address those scenarios we'll take an idea from the pdp11 port for describing the restriction in constraints as well. To implement that we need register classes and constraints which are "all general purpose hardware registers except r0". And similarly for r1..r7(sp). This patch adds those register classes and constraints, but does not yet use them. Pushed to the trunk. Jeff commit 6366e3e8847af98d4728d55951534769d034d02a Author: Jeff Law <jeffreyalaw@gmail.com> Date: Sun Oct 16 12:43:25 2022 -0400 Add new constraints for upcoming autoinc fixes GCC does not allow a the operand of an autoinc addressing mode to overlap with another soure operand in the same insn. This is primarly enforced with insn conditions. However, cases can slip through LRA and reload. To address those scenarios we'll take an idea from the pdp11 port for describing the restriction in constraints as well. To implement that we need register classes and constraints which are "all general purpose hardware registers except r0". And similarly for r1..r7(sp). This patch adds those register classes and constraints, but does not yet use them. gcc/ * config/h8300/constraints.md (Z0..Z7): New register constraints. * config/h8300/h8300.h (reg_class): Add new classes. (REG_CLASS_NAMES): Similarly. (REG_CLASS_CONTENTS): Similarly.