From patchwork Wed Sep 27 17:56:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pat Haugen X-Patchwork-Id: 819256 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-463070-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="GySwWvd6"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y2QVd0Ctmz9t3m for ; Thu, 28 Sep 2017 03:56:22 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:date:mime-version:content-type:message-id; q=dns; s=default; b=pKOVqLjIvWldhWeBSaL5X4d4STIAcJiNahGQsFyrKnUEd2SSdf NsDnYqZ9pPhhCHXpjhtga3qV9WTZ0p1g6uDQh+5bVQgE26sdg/wZqgtaPn3kvO3p 0wvhu/HECgt5iucCQ8VWardadK8ZC+5YjlXyDaltILpX/SN1qAQgcffUA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:date:mime-version:content-type:message-id; s= default; bh=wmXJMfD9EfwYz2F7UrhWFIHNo1g=; b=GySwWvd6/I/SnKVFlk8w jjk60AI591Ys0UzG+96dO7d5TWWKhcUdbI1Uy9ChL4wAIx7dRI9NUo8qNVBsujRf 3Pn57mjZbv359JYngIwRv4M8xX/Fc6MHab4KUglJu3UOvxPzHWvbFPmFvv8obH28 D2cA2/NLLggAtS++/mZ3mtM= Received: (qmail 69469 invoked by alias); 27 Sep 2017 17:56:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 69460 invoked by uid 89); 27 Sep 2017 17:56:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=dispatch, H*MI:7591 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 27 Sep 2017 17:56:13 +0000 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v8RHnOpY140709 for ; Wed, 27 Sep 2017 13:56:08 -0400 Received: from e17.ny.us.ibm.com (e17.ny.us.ibm.com [129.33.205.207]) by mx0a-001b2d01.pphosted.com with ESMTP id 2d8fpmm7p8-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 27 Sep 2017 13:56:07 -0400 Received: from localhost by e17.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 27 Sep 2017 13:56:05 -0400 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v8RHu46p38994004; Wed, 27 Sep 2017 17:56:04 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6672012404C; Wed, 27 Sep 2017 13:53:19 -0400 (EDT) Received: from oc1687012634.ibm.com (unknown [9.10.86.65]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP id 39F5F12403D; Wed, 27 Sep 2017 13:53:19 -0400 (EDT) To: GCC Patches Cc: Segher Boessenkool , David Edelsohn From: Pat Haugen Subject: [PATCH, rs6000] Correct some Power9 scheduling info Date: Wed, 27 Sep 2017 12:56:03 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17092717-0040-0000-0000-000003A9175F X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007800; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000232; SDB=6.00923205; UDB=6.00464095; IPR=6.00703347; BA=6.00005609; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017293; XFM=3.00000015; UTC=2017-09-27 17:56:06 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17092717-0041-0000-0000-0000079E21EB Message-Id: <0fbdce8d-64c5-81b9-7591-9a664bffc926@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-09-27_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709270247 X-IsSubscribed: yes The following patch corrects some Power9 resource requirements and instruction latencies. Bootstrap/regtest on powerpc64le-linux with no new regressions. Ok for trunk? -Pat 2017-09-27 Pat Haugen * config/rs6000/power9.md (DU_C2_3_power9): Remove an incorrect combination. (power9-alu): Split out insert/shift types... (power9-rot): ... to here. Correct dispatch resources. (power9-cracked-alu): Correct dispatch resources. (power9-mul): Likewise. (power9-mul-compare): Likewise. (power9-fp): Correct latency. (power9-ddiv): Likewise. (power9-vecfdiv): Likewise. (power9-vecdiv): Likewise. Index: gcc/config/rs6000/power9.md =================================================================== --- gcc/config/rs6000/power9.md (revision 252029) +++ gcc/config/rs6000/power9.md (working copy) @@ -80,7 +80,6 @@ (define_reservation "DU_C2_power9" "x0_p ; 2-way cracked plus 3rd slot (define_reservation "DU_C2_3_power9" "x0_power9+x1_power9+xa0_power9| x1_power9+x2_power9+xa0_power9| - x1_power9+x2_power9+xb0_power9| x2_power9+x3_power9+xb0_power9") ; 3-way cracked (consumes whole decode/dispatch cycle) @@ -243,21 +242,29 @@ (define_insn_reservation "power9-sync" 4 ; Most ALU insns are simple 2 cycle, including record form (define_insn_reservation "power9-alu" 2 - (and (ior (eq_attr "type" "add,exts,integer,logical,isel") - (and (eq_attr "type" "insert,shift") - (eq_attr "dot" "no"))) + (and (eq_attr "type" "add,exts,integer,logical,isel") (eq_attr "cpu" "power9")) "DU_any_power9,VSU_power9") ; 5 cycle CR latency (define_bypass 5 "power9-alu" "power9-crlogical,power9-mfcr,power9-mfcrf") +; Rotate/shift prevent use of third slot +(define_insn_reservation "power9-rot" 2 + (and (eq_attr "type" "insert,shift") + (eq_attr "dot" "no") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,VSU_power9") +; 5 cycle CR latency +(define_bypass 5 "power9-rot" + "power9-crlogical,power9-mfcr,power9-mfcrf") + ; Record form rotate/shift are cracked (define_insn_reservation "power9-cracked-alu" 2 (and (eq_attr "type" "insert,shift") (eq_attr "dot" "yes") (eq_attr "cpu" "power9")) - "DU_C2_power9,VSU_power9") + "DU_C2_3_power9,VSU_power9") ; 7 cycle CR latency (define_bypass 7 "power9-cracked-alu" "power9-crlogical,power9-mfcr,power9-mfcrf") @@ -291,13 +298,13 @@ (define_insn_reservation "power9-mul" 5 (and (eq_attr "type" "mul") (eq_attr "dot" "no") (eq_attr "cpu" "power9")) - "DU_any_power9,VSU_power9") + "DU_slice_3_power9,VSU_power9") (define_insn_reservation "power9-mul-compare" 5 (and (eq_attr "type" "mul") (eq_attr "dot" "yes") (eq_attr "cpu" "power9")) - "DU_C2_power9,VSU_power9") + "DU_C2_3_power9,VSU_power9") ; 10 cycle CR latency (define_bypass 10 "power9-mul-compare" "power9-crlogical,power9-mfcr,power9-mfcrf") @@ -349,7 +356,7 @@ (define_insn_reservation "power9-fpsimpl (eq_attr "cpu" "power9")) "DU_slice_3_power9,VSU_power9") -(define_insn_reservation "power9-fp" 7 +(define_insn_reservation "power9-fp" 5 (and (eq_attr "type" "fp,dmul") (eq_attr "cpu" "power9")) "DU_slice_3_power9,VSU_power9") @@ -366,7 +373,7 @@ (define_insn_reservation "power9-sdiv" 2 (eq_attr "cpu" "power9")) "DU_slice_3_power9,VSU_power9") -(define_insn_reservation "power9-ddiv" 33 +(define_insn_reservation "power9-ddiv" 27 (and (eq_attr "type" "ddiv") (eq_attr "cpu" "power9")) "DU_slice_3_power9,VSU_power9") @@ -419,12 +426,12 @@ (define_insn_reservation "power9-veccomp (eq_attr "cpu" "power9")) "DU_super_power9,VSU_super_power9") -(define_insn_reservation "power9-vecfdiv" 28 +(define_insn_reservation "power9-vecfdiv" 24 (and (eq_attr "type" "vecfdiv") (eq_attr "cpu" "power9")) "DU_super_power9,VSU_super_power9") -(define_insn_reservation "power9-vecdiv" 32 +(define_insn_reservation "power9-vecdiv" 27 (and (eq_attr "type" "vecdiv") (eq_attr "size" "!128") (eq_attr "cpu" "power9"))