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[61.216.141.121]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a65c200b00288628acf6dsm5376875pjs.14.2024.01.07.22.16.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 07 Jan 2024 22:16:38 -0800 (PST) Message-ID: <0c5c7a33-93c9-46ad-85f3-b6f4bb3d5ddd@gmail.com> Date: Mon, 8 Jan 2024 14:16:37 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: gcc-patches , Kyrylo Tkachov , Richard Earnshaw Cc: "Jason.Wu@anshingtek.com.tw" From: Chung-Ju Wu Subject: [PATCH 2/2] arm: Add cortex-m52 doc X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, This is the patch to add cortex-m52 in the Arm-related options sections of the gcc invoke.texi documentation. Is it OK for trunk? Regards, jasonwucj From b7ce3d499d4bf087ec54a5f834876c9108d46c3d Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Thu, 7 Dec 2023 11:26:25 +0800 Subject: [PATCH 2/2] arm: Add Arm Cortex-M52 CPU documentation. Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * doc/invoke.texi: Update docs. --- gcc/doc/invoke.texi | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d71583853f0..bdbe0074cb4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -23094,7 +23094,7 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-r52plus}, @samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3}, @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33}, -@samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1}, +@samp{cortex-m35p}, @samp{cortex-m52}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1}, @samp{cortex-x1c}, @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply}, @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4}, @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale}, @@ -23160,34 +23160,34 @@ The following extension options are common to the listed CPUs: @table @samp @item +nodsp Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}, -@samp{cortex-m55} and @samp{cortex-m85}. Also disable the M-Profile Vector -Extension (MVE) integer and single precision floating-point instructions on -@samp{cortex-m55} and @samp{cortex-m85}. +@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. +Also disable the M-Profile Vector Extension (MVE) integer and +single precision floating-point instructions on +@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. @item +nopacbti Disable the Pointer Authentication and Branch Target Identification Extension -on @samp{cortex-m85}. +on @samp{cortex-m52} and @samp{cortex-m85}. @item +nomve Disable the M-Profile Vector Extension (MVE) integer and single precision -floating-point instructions on @samp{cortex-m55} and @samp{cortex-m85}. +floating-point instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. @item +nomve.fp Disable the M-Profile Vector Extension (MVE) single precision floating-point -instructions on @samp{cortex-m55} and @samp{cortex-m85}. +instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. @item +cdecp0, +cdecp1, ... , +cdecp7 Enable the Custom Datapath Extension (CDE) on selected coprocessors according -to the numbers given in the options in the range 0 to 7 on @samp{cortex-m55}. +to the numbers given in the options in the range 0 to 7 on @samp{cortex-m52} and @samp{cortex-m55}. @item +nofp Disables the floating-point instructions on @samp{arm9e}, @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s}, @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, -@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p} @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p}, -@samp{cortex-m55} and @samp{cortex-m85}. +@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}. Disables the floating-point and SIMD instructions on @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12}, @@ -23530,9 +23530,9 @@ Development Tools Engineering Specification", which can be found on Mitigate against a potential security issue with the @code{VLLDM} instruction in some M-profile devices when using CMSE (CVE-2021-365465). This option is enabled by default when the option @option{-mcpu=} is used with -@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55}, @code{cortex-m85} -or @code{star-mc1}. The option @option{-mno-fix-cmse-cve-2021-35465} can be used -to disable the mitigation. +@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m52}, @code{cortex-m55}, +@code{cortex-m85} or @code{star-mc1}. The option @option{-mno-fix-cmse-cve-2021-35465} +can be used to disable the mitigation. @opindex mstack-protector-guard @opindex mstack-protector-guard-offset