From patchwork Tue Feb 4 02:26:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 1233104 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-518831-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=Su5OUbAw; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48BT9Q5xHRz9sX3 for ; Tue, 4 Feb 2020 13:27:06 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=mQND5o2kjRPOsmQyNRK P3WibUh76MeXvYivH8IBxAhzQzWFzQorHRDRbzXkeUbjoqay4i5uNHYn+KIKME07 awIKL9VWIECIZa4EdKzQS+ohGBRLIqqeFAatvoRNH6h27pgog8ERMTX8Ljwi0fhm x9n999e1bnwjg7YVwLeEahY8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=hVUDgew9vJywa8o9JmOfrWnnI V4=; b=Su5OUbAwbYdqa4IH8NQXtFe7m70aFoHl5qyO53RVeAXjPFWToi5A81f+s iNgJyibdK2q/JTdAXClu2BKvu0b5qKKGOaI0GLgesigJTWdwpRkpWmg0LdYxypSs foXKRSRQzHeOb2CB959GBpfKAjZQHt6ShNsNoK+o+PV5uVJLss= Received: (qmail 63386 invoked by alias); 4 Feb 2020 02:26:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 63308 invoked by uid 89); 4 Feb 2020 02:26:54 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 04 Feb 2020 02:26:49 +0000 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0142PlWL087642; Mon, 3 Feb 2020 21:26:48 -0500 Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0a-001b2d01.pphosted.com with ESMTP id 2xxbmnp058-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 03 Feb 2020 21:26:48 -0500 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id 0142MCtK015124; Tue, 4 Feb 2020 02:26:47 GMT Received: from b03cxnp08027.gho.boulder.ibm.com (b03cxnp08027.gho.boulder.ibm.com [9.17.130.19]) by ppma02wdc.us.ibm.com with ESMTP id 2xw0y65scg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Feb 2020 02:26:47 +0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0142QkZk51446250 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Feb 2020 02:26:46 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9F89CC6057; Tue, 4 Feb 2020 02:26:46 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7781CC6055; Tue, 4 Feb 2020 02:26:46 +0000 (GMT) Received: from localhost (unknown [9.40.194.84]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 4 Feb 2020 02:26:46 +0000 (GMT) From: Bill Schmidt To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org Subject: [PATCH 02/14] Add stubs for input files. These will grow much larger. Date: Mon, 3 Feb 2020 20:26:03 -0600 Message-Id: <0a94b20d0ca902a1a3966a219105e0a115a8e7c3.1580782131.git.wschmidt@linux.ibm.com> In-Reply-To: References: In-Reply-To: References: This patch adds a subset of the builtin and overload descriptions. I've also started annotating the old-style descriptions in rs6000-c.c where I'm deliberately not planning to support new versions of them. We may have to have some discussion around these at some point, but this helps me track this as I move through the transition. 2020-02-03 Bill Schmidt * config/rs6000/rs6000-bif.def: New file. * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Annotate some deprecated and bogus entries. * config/rs6000/rs6000-overload.def: New file. --- gcc/config/rs6000/rs6000-bif.def | 187 ++++++++++++++++++++++++++ gcc/config/rs6000/rs6000-call.c | 35 +++++ gcc/config/rs6000/rs6000-overload.def | 5 + 3 files changed, 227 insertions(+) create mode 100644 gcc/config/rs6000/rs6000-bif.def create mode 100644 gcc/config/rs6000/rs6000-overload.def diff --git a/gcc/config/rs6000/rs6000-bif.def b/gcc/config/rs6000/rs6000-bif.def new file mode 100644 index 00000000000..85196400993 --- /dev/null +++ b/gcc/config/rs6000/rs6000-bif.def @@ -0,0 +1,187 @@ +[TARGET_ALTIVEC] + math vf __builtin_altivec_vmaddfp (vf, vf, vf); + VMADDFP fmav4sf4 {} + vss __builtin_altivec_vmhaddshs (vss, vss, vss); + VMHADDSHS altivec_vmhaddshs {} + vss __builtin_altivec_vmhraddshs (vss, vss, vss); + VMHRADDSHS altivec_vmhraddshs {} + const vss __builtin_altivec_vmladduhm (vss, vss, vss); + VMLADDUHM fmav8hi4 {} + const vui __builtin_altivec_vmsumubm (vuc, vuc, vui); + VMSUMUBM altivec_vmsumubm {} + const vsi __builtin_altivec_vmsummbm (vsc, vuc, vsi); + VMSUMMBM altivec_vmsummbm {} + const vui __builtin_altivec_vmsumuhm (vus, vus, vui); + VMSUMUHM altivec_vmsumuhm {} + const vsi __builtin_altivec_vmsumshm (vss, vss, vsi); + VMSUMSHM altivec_vmsumshm {} + vui __builtin_altivec_vmsumuhs (vus, vus, vui); + VMSUMUHS altivec_vmsumuhs {} + vsi __builtin_altivec_vmsumshs (vss, vss, vsi); + VMSUMSHS altivec_vmsumshs {} + math vf __builtin_altivec_vnmsubfp (vf, vf, vf); + VNMSUBFP nfmsv4sf4 {} + const vsq __builtin_altivec_vperm_1ti (vsq, vsq, vuc); + VPERM_1TI altivec_vperm_v1ti {} + const vf __builtin_altivec_vperm_4sf (vf, vf, vuc); + VPERM_4SF altivec_vperm_v4sf {} + const vsi __builtin_altivec_vperm_4si (vsi, vsi, vuc); + VPERM_4SI altivec_vperm_v4si {} + const vss __builtin_altivec_vperm_8hi (vss, vss, vuc); + VPERM_8HI altivec_vperm_v8hi {} + const vsc __builtin_altivec_vperm_16qi (vsc, vsc, vuc); + VPERM_16QI altivec_vperm_v16qi {} + const vuq __builtin_altivec_vperm_1ti_uns (vuq, vuq, vuc); + VPERM_1TI_UNS altivec_vperm_v1ti_uns {} + const vui __builtin_altivec_vperm_4si_uns (vui, vui, vuc); + VPERM_4SI_UNS altivec_vperm_v4si_uns {} + const vus __builtin_altivec_vperm_8hi_uns (vus, vus, vuc); + VPERM_8HI_UNS altivec_vperm_v8hi_uns {} + const vuc __builtin_altivec_vperm_16qi_uns (vuc, vuc, vuc); + VPERM_16QI_UNS altivec_vperm_v16qi_uns {} + const vf __builtin_altivec_vsel_4sf (vf, vf, vbi); + VSEL_4SF_B vector_select_v4sf {} + const vf __builtin_altivec_vsel_4sf (vf, vf, vui); + VSEL_4SF_U vector_select_v4sf {} + const vsi __builtin_altivec_vsel_4si (vsi, vsi, vbi); + VSEL_4SI_B vector_select_v4si {} + const vsi __builtin_altivec_vsel_4si (vsi, vsi, vui); + VSEL_4SI_U vector_select_v4si {} + const vui __builtin_altivec_vsel_4si (vui, vui, vbi); + VSEL_4SI_UB vector_select_v4si {} + const vui __builtin_altivec_vsel_4si (vui, vui, vui); + VSEL_4SI_UU vector_select_v4si {} + const vbi __builtin_altivec_vsel_4si (vbi, vbi, vbi); + VSEL_4SI_BB vector_select_v4si {} + const vbi __builtin_altivec_vsel_4si (vbi, vbi, vui); + VSEL_4SI_BU vector_select_v4si {} + const vss __builtin_altivec_vsel_8hi (vss, vss, vbs); + VSEL_8HI_B vector_select_v8hi {} + const vss __builtin_altivec_vsel_8hi (vss, vss, vus); + VSEL_8HI_U vector_select_v8hi {} + const vus __builtin_altivec_vsel_8hi (vus, vus, vbs); + VSEL_8HI_UB vector_select_v8hi {} + const vus __builtin_altivec_vsel_8hi (vus, vus, vus); + VSEL_8HI_UU vector_select_v8hi {} + const vbs __builtin_altivec_vsel_8hi (vbs, vbs, vbs); + VSEL_8HI_BB vector_select_v8hi {} + const vbs __builtin_altivec_vsel_8hi (vbs, vbs, vus); + VSEL_8HI_BU vector_select_v8hi {} + const vsc __builtin_altivec_vsel_16qi (vsc, vsc, vbc); + VSEL_16QI_B vector_select_v16qi {} + const vsc __builtin_altivec_vsel_16qi (vsc, vsc, vuc); + VSEL_16QI_U vector_select_v16qi {} + const vuc __builtin_altivec_vsel_16qi (vuc, vuc, vbc); + VSEL_16QI_UB vector_select_v16qi {} + const vuc __builtin_altivec_vsel_16qi (vuc, vuc, vuc); + VSEL_16QI_UU vector_select_v16qi {} + const vbc __builtin_altivec_vsel_16qi (vbc, vbc, vbc); + VSEL_16QI_BB vector_select_v16qi {} + const vbc __builtin_altivec_vsel_16qi (vbc, vbc, vuc); + VSEL_16QI_BU vector_select_v16qi {} + const vsq __builtin_altivec_vsel_1ti (vsq, vsq, vuq); + VSEL_1TI vector_select_v1ti {} + const vui __builtin_altivec_vsel_4si_uns (vui, vui, vui); + VSEL_4SI_UNS vector_select_v4si_uns {} + const vus __builtin_altivec_vsel_8hi_uns (vus, vus, vus); + VSEL_8HI_UNS vector_select_v8hi_uns {} + const vuc __builtin_altivec_vsel_16qi_uns (vuc, vuc, vuc); + VSEL_16QI_UNS vector_select_v16qi_uns {} + const vsc __builtin_altivec_vsldoi_16qi (vsc, vsc, const int<4>); + VSLDOI_16QI altivec_vsldoi_v16qi {} + const vuc __builtin_altivec_vsldoi_16qi (vuc, vuc, const int<4>); + VSLDOI_16QI_U altivec_vsldoi_v16qi {} + const vbc __builtin_altivec_vsldoi_16qi (vbc, vbc, const int<4>); + VSLDOI_16QI_B altivec_vsldoi_v16qi {} + const vss __builtin_altivec_vsldoi_8hi (vss, vss, const int<4>); + VSLDOI_8HI altivec_vsldoi_v8hi {} + const vus __builtin_altivec_vsldoi_8hi (vus, vus, const int<4>); + VSLDOI_8HI_U altivec_vsldoi_v8hi {} + const vbs __builtin_altivec_vsldoi_8hi (vbs, vbs, const int<4>); + VSLDOI_8HI_B altivec_vsldoi_v8hi {} + const vp __builtin_altivec_vsldoi_8hi (vp, vp, const int<4>); + VSLDOI_8HI_P altivec_vsldoi_v8hi {} + const vsi __builtin_altivec_vsldoi_4si (vsi, vsi, const int<4>); + VSLDOI_4SI altivec_vsldoi_v4si {} + const vui __builtin_altivec_vsldoi_4si (vui, vui, const int<4>); + VSLDOI_4SI_U altivec_vsldoi_v4si {} + const vbi __builtin_altivec_vsldoi_4si (vbi, vbi, const int<4>); + VSLDOI_4SI_B altivec_vsldoi_v4si {} + const vuq __builtin_altivec_vsel_1ti_uns (vuq, vuq, vuq); + VSEL_1TI_UNS vector_select_v1ti_uns {} + const vf __builtin_altivec_vsldoi_4sf (vf, vf, const int<4>); + VSLDOI_4SF altivec_vsldoi_v4sf {} + void __builtin_altivec_dst (void *, const int, const int<2>); + DST altivec_dst {} + void __builtin_altivec_dstt (void *, const int, const int<2>); + DSTT altivec_dstt {} + void __builtin_altivec_dstst (void *, const int, const int<2>); + DSTST altivec_dstst {} + void __builtin_altivec_dststt (void *, const int, const int<2>); + DSTSTT altivec_dststt {} + const vsc __builtin_altivec_vaddubm (vsc, vsc); + VADDUBM addv16qi3 {} + const vuc __builtin_altivec_vaddubm (vuc, vuc); + VADDUBM_U addv16qi3 {} + const vss __builtin_altivec_vadduhm (vss, vss); + VADDUHM addv8hi3 {} + const vus __builtin_altivec_vadduhm (vus, vus); + VADDUHM_U addv8hi3 {} + const vsi __builtin_altivec_vadduwm (vsi, vsi); + VADDUWM addv4si3 {} + const vui __builtin_altivec_vadduwm (vui, vui); + VADDUWM_U addv4si3 {} + const vf __builtin_altivec_vaddfp (vf, vf); + VADDFP addv4sf3 {} + const vsi __builtin_altivec_vaddcuw (vsi, vsi); + VADDCUW altivec_vaddcuw {} + const vui __builtin_altivec_vaddcuw (vui, vui); + VADDCUW_U altivec_vaddcuw {} + const vuc __builtin_altivec_vaddubs (vuc, vuc); + VADDUBS altivec_vaddubs {} + const vsc __builtin_altivec_vaddsbs (vsc, vsc); + VADDSBS altivec_vaddsbs {} + const vus __builtin_altivec_vadduhs (vus, vus); + VADDUHS altivec_vadduhs {} + const vss __builtin_altivec_vaddshs (vss, vss); + VADDSHS altivec_vaddshs {} + const vui __builtin_altivec_vadduws (vui, vui); + VADDUWS altivec_vadduws {} + const vsi __builtin_altivec_vaddsws (vsi, vsi); + VADDSWS altivec_vaddsws {} + const vbc __builtin_altivec_vand_v16qi_uns (vbc, vbc); + VAND_V16QI_UNS_B andv16qi3 {} + const vuc __builtin_altivec_vand_v16qi_uns (vuc, vuc); + VAND_V16QI_UNS andv16qi3 {} + const vbc __builtin_altivec_vand_v16qi (vbc, vbc); + VAND_V16QI_B andv16qi3 {} + const vsc __builtin_altivec_vand_v16qi (vsc, vsc); + VAND_V16QI andv16qi3 {} + const vsc __builtin_altivec_abs_v16qi (vsc); + ABS_V16QI absv16qi2 {abs} + const vss __builtin_altivec_abs_v8hi (vss); + ABS_V8HI absv8hi2 {abs} + +[VSX] + const vd __builtin_altivec_vperm_2df (vd, vd, vuc); + VPERM_2DF altivec_vperm_v2df {} + const vsll __builtin_altivec_vperm_2di (vsll, vsll, vuc); + VPERM_2DI altivec_vperm_v2di {} + const vull __builtin_altivec_vperm_2di_uns (vull, vull, vuc); + VPERM_2DI_UNS altivec_vperm_v2di_uns {} + const vd __builtin_altivec_vsel_2df (vd, vd, vbll); + VSEL_2DF_B vector_select_v2df {} + const vd __builtin_altivec_vsel_2df (vd, vd, vull); + VSEL_2DF_U vector_select_v2df {} + const vsll __builtin_altivec_vsel_2di (vsll, vsll, vsll, vbll); + VSEL_2DI_B vector_select_v2di {} + const vull __builtin_altivec_vsel_2di_uns (vull, vull, vull); + VSEL_2DI_UNS vector_select_v2di_uns {} + const vsll __builtin_altivec_vsldoi_2di (vsll, vsll, const int<4>); + VSLDOI_2DI altivec_vsldoi_v2di {} + const vull __builtin_altivec_vsldoi_2di (vull, vull, const int<4>); + VSLDOI_2DI_U altivec_vsldoi_v2di {} + const vbll __builtin_altivec_vsldoi_2di (vbll, vbll, const int<4>); + VSLDOI_2DI_B altivec_vsldoi_v2di {} + const vd __builtin_altivec_vsldoi_2df (vd, vd, const int<4>); + VSLDOI_2DF altivec_vsldoi_v2df {} diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 59060647431..57b0e07898e 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -429,36 +429,42 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, /* Binary AltiVec/VSX builtins. */ + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, @@ -490,12 +496,14 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + /* Next 4 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, @@ -506,12 +514,14 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, + /* Next 4 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, @@ -522,12 +532,14 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + /* Next 24 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, @@ -551,18 +563,21 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, @@ -571,10 +586,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, @@ -583,54 +600,64 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, @@ -684,20 +711,24 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, + /* Next one deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, + /* Next one deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + /* Next 2 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, @@ -3145,6 +3176,7 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI }, + /* Next 2 appear bogus, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, @@ -3153,12 +3185,14 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI }, + /* Next 1 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + /* Next 1 deprecated, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, @@ -3171,6 +3205,7 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI }, + /* Next 2 appear bogues, not in rs6000-bif.def. */ { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def new file mode 100644 index 00000000000..e3149d661fa --- /dev/null +++ b/gcc/config/rs6000/rs6000-overload.def @@ -0,0 +1,5 @@ +[VEC_ABS, vec_abs, __builtin_vec_abs] + vsc __builtin_vec_abs (vsc); + ABS_V16QI + vss __builtin_vec_abs (vss); + ABS_V8HI