From patchwork Wed Jun 4 21:44:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bennett X-Patchwork-Id: 356113 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4657314008F for ; Thu, 5 Jun 2014 07:45:06 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:content-transfer-encoding:mime-version; q=dns; s= default; b=fcXZK6N7bgyx85LuoZuNKYyolCNuapVsaRU14hy9QodTsk9v4dwuC 5mukyAzpXMd+CK0ZBmw62QVotQ4xXoH5PgiVnuXwYh9rYXQPfYWfPVlWuxwudmxs YBQQvXzXpDKNr7Q5q5e5xW1IdB6CgJ6bFb4FF8j0c58hCPpzdEZ9pU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:content-transfer-encoding:mime-version; s=default; bh=gwjeB5ykmT9NvecdQeNFJCbvKrQ=; b=xnUmJphT+/Lc9r3t5xWNVZAZIeqH 5+55X8twFNQ2Ykv+jp3xps8877pOZ2Yzmf7+vSqeYa0Ov535fZLrazVVGfrb2HN+ DvjxX1qLr0zenE+XIAWfGKdbLJBchf5uZ/GFYu6gC1MkjwBoHuOc1gald/G6ERIy Sr74K1OuG0PnCLk= Received: (qmail 22839 invoked by alias); 4 Jun 2014 21:44:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22824 invoked by uid 89); 4 Jun 2014 21:44:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.4 required=5.0 tests=AWL, BAYES_50, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 04 Jun 2014 21:44:54 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 8ECF852E073E5; Wed, 4 Jun 2014 22:44:45 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.181.6; Wed, 4 Jun 2014 22:44:49 +0100 Received: from LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9]) by LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9%17]) with mapi id 14.03.0174.001; Wed, 4 Jun 2014 22:44:48 +0100 From: Andrew Bennett To: Richard Sandiford , Jaydeep Patil CC: Rich Fuhler , Matthew Fortune , "gcc-patches@gcc.gnu.org" Subject: RE: [PATCH][MIPS] P5600 scheduling Date: Wed, 4 Jun 2014 21:44:47 +0000 Message-ID: <0DA23CC379F5F945ACB41CF394B982775855BC@LEMAIL01.le.imgtec.org> References: <87r43pjx4f.fsf@talisman.default> <87lhtqf82l.fsf@talisman.default> <87oayixmst.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> In-Reply-To: <87oayixmst.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> MIME-Version: 1.0 X-IsSubscribed: yes > -----Original Message----- > From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-owner@gcc.gnu.org] On > Behalf Of Richard Sandiford > Sent: 28 May 2014 10:42 > To: Jaydeep Patil > Cc: Rich Fuhler; Matthew Fortune; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH][MIPS] P5600 scheduling > > Jaydeep Patil writes: > > Please refer to the attached patch files. > > > > gcc-p5600-noMSA.patch > > TARGET_P5600 has been removed > > Sorry, noticed one other thing: > > > +bool > > +mips_fmadd_bypass (rtx out_insn, rtx in_insn) > > +{ > > + int dst_reg, src_reg; > > + > > + gcc_assert (get_attr_type (in_insn) == TYPE_FMADD); > > + gcc_assert (get_attr_type (out_insn) == TYPE_FMADD); > > + > > + if (recog_memoized (in_insn) < 0 > > + || recog_memoized (out_insn) < 0) > > + return false; > > What I meant with the assertions vs. recog_memoized is that > get_attr_type (...) == TYPE_FMADD only holds if the instructions > are recognisable. Once you've asserted that the types are correct, > the following: > > if (recog_memoized (in_insn) < 0 > || recog_memoized (out_insn) < 0) > return false; > > is dead code. The patch is OK with the recog_memoized calls removed. > No need to repost the patch; just commit it with that change once > the copyright log-jam is sorted out. I was just about to commit this patch for Jaydeep, when I found a few issues. Firstly, the mips-tables.opt file was not regenerated. Secondly, I have changed invoke.texi to document the -march=p5600 option. Thirdly, binutils defines p5600 as mip32r5, not mips32r2, (which was causing assembler errors if you build using the -march=p5600 gcc command line option). I have updated the MIPS_ISA_LEVEL_SPEC to map -march=p5600 to -mips32r5, and made the PROCESSOR_P5600 use the MIPS32r5 ISA value. Finally I have updated the processor for mips32r5 entry to use p5600 rather than 74k. The updated patch and ChangeLog are shown below. Ok to commit? Many thanks, Andrew ChangeLog: 2014-06-04 Jaydeep Patil Prachi Godbole * config/mips/mips-cpus.def: Add definition for p5600. Updated mips32r5 entry to use PROCESSOR_P5600. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips-protos.h (mips_fmadd_bypass): Add prototype. * config/mips/mips.c (mips_fmadd_bypass): New function. (mips_rtx_cost_data): Add costs for p5600. (mips_issue_rate): Add support for p5600. (mips_multipass_dfa_lookahead): Likewise. * config/mips/mips.h (TUNE_P5600): New define. (TUNE_MACC_CHAINS): Add TUNE_P5600. (MIPS_ISA_LEVEL_SPEC): Map -march=p5600 to -mips32r5. * config/mips/mips.md: Include p5600.md. (processor): Add p5600. * config/mips/p5600.md: New file. Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 211230) +++ gcc/doc/invoke.texi (working copy) @@ -17191,6 +17191,7 @@ @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{orion}, +@samp{p5600}, @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400}, @samp{r4600}, @samp{r4650}, @samp{r4700}, @samp{r6000}, @samp{r8000}, @samp{rm7000}, @samp{rm9000}, Index: gcc/config/mips/mips-tables.opt =================================================================== --- gcc/config/mips/mips-tables.opt (revision 211230) +++ gcc/config/mips/mips-tables.opt (working copy) @@ -619,50 +619,53 @@ Enum(mips_arch_opt_value) String(r1004kf1_1) Value(82) EnumValue -Enum(mips_arch_opt_value) String(5kc) Value(83) Canonical +Enum(mips_arch_opt_value) String(p5600) Value(83) Canonical EnumValue -Enum(mips_arch_opt_value) String(r5kc) Value(83) +Enum(mips_arch_opt_value) String(5kc) Value(84) Canonical EnumValue -Enum(mips_arch_opt_value) String(5kf) Value(84) Canonical +Enum(mips_arch_opt_value) String(r5kc) Value(84) EnumValue -Enum(mips_arch_opt_value) String(r5kf) Value(84) +Enum(mips_arch_opt_value) String(5kf) Value(85) Canonical EnumValue -Enum(mips_arch_opt_value) String(20kc) Value(85) Canonical +Enum(mips_arch_opt_value) String(r5kf) Value(85) EnumValue -Enum(mips_arch_opt_value) String(r20kc) Value(85) +Enum(mips_arch_opt_value) String(20kc) Value(86) Canonical EnumValue -Enum(mips_arch_opt_value) String(sb1) Value(86) Canonical +Enum(mips_arch_opt_value) String(r20kc) Value(86) EnumValue -Enum(mips_arch_opt_value) String(sb1a) Value(87) Canonical +Enum(mips_arch_opt_value) String(sb1) Value(87) Canonical EnumValue -Enum(mips_arch_opt_value) String(sr71000) Value(88) Canonical +Enum(mips_arch_opt_value) String(sb1a) Value(88) Canonical EnumValue -Enum(mips_arch_opt_value) String(sr71k) Value(88) +Enum(mips_arch_opt_value) String(sr71000) Value(89) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlr) Value(89) Canonical +Enum(mips_arch_opt_value) String(sr71k) Value(89) EnumValue -Enum(mips_arch_opt_value) String(loongson3a) Value(90) Canonical +Enum(mips_arch_opt_value) String(xlr) Value(90) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(91) Canonical +Enum(mips_arch_opt_value) String(loongson3a) Value(91) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(92) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(92) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(93) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(93) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(94) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(94) Canonical +EnumValue +Enum(mips_arch_opt_value) String(xlp) Value(95) Canonical + Index: gcc/config/mips/mips.md =================================================================== --- gcc/config/mips/mips.md (revision 211230) +++ gcc/config/mips/mips.md (working copy) @@ -65,6 +65,7 @@ sr71000 xlr xlp + p5600 ]) (define_c_enum "unspec" [ @@ -1050,6 +1051,7 @@ (eq_attr "type" "ghost") "nothing") +(include "p5600.md") (include "4k.md") (include "5k.md") (include "20kc.md") Index: gcc/config/mips/p5600.md =================================================================== --- gcc/config/mips/p5600.md (revision 0) +++ gcc/config/mips/p5600.md (revision 0) @@ -0,0 +1,204 @@ +;; DFA-based pipeline description for P5600. +;; +;; Copyright (C) 2007-2014 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_automaton "p5600_agen_pipe, p5600_alu_pipe, p5600_fpu_pipe") + +;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes +(define_cpu_unit "p5600_agq, p5600_al2, p5600_ctistd, p5600_ldsta, + p5600_gpdiv" "p5600_agen_pipe") + +;; The arithmetic-logic-unit queue (ALQ) has ALU pipe +(define_cpu_unit "p5600_alq, p5600_alu" "p5600_alu_pipe") + +;; The floating-point-unit queue (FPQ) has short and long pipes +(define_cpu_unit "p5600_fpu_short, p5600_fpu_long" "p5600_fpu_pipe") + +;; Short FPU pipeline +(define_cpu_unit "p5600_fpu_store" "p5600_fpu_pipe") + +;; Long FPU pipeline +(define_cpu_unit "p5600_fpu_apu" "p5600_fpu_pipe") + +(define_reservation "p5600_agq_al2" "p5600_agq, p5600_al2") +(define_reservation "p5600_agq_ctistd" "p5600_agq, p5600_ctistd") +(define_reservation "p5600_agq_ldsta" "p5600_agq, p5600_ldsta") +(define_reservation "p5600_alq_alu" "p5600_alq, p5600_alu") + +;; +;; FPU pipe +;; + +;; fadd, fsub +(define_insn_reservation "p5600_fpu_fadd" 4 + (eq_attr "type" "fadd,fabs,fneg") + "p5600_fpu_long, p5600_fpu_apu") + +;; fabs, fneg, fcmp +(define_insn_reservation "p5600_fpu_fabs" 2 + (eq_attr "type" "fabs,fneg,fcmp,fmove") + "p5600_fpu_short, p5600_fpu_apu") + +;; fload +(define_insn_reservation "p5600_fpu_fload" 8 + (eq_attr "type" "fpload,fpidxload") + "p5600_fpu_long, p5600_fpu_apu") + +;; fstore +(define_insn_reservation "p5600_fpu_fstore" 1 + (eq_attr "type" "fpstore,fpidxstore") + "p5600_fpu_short, p5600_fpu_apu") + +;; fmadd +(define_insn_reservation "p5600_fpu_fmadd" 9 + (eq_attr "type" "fmadd") + "p5600_fpu_long, p5600_fpu_apu") + +;; fmul +(define_insn_reservation "p5600_fpu_fmul" 5 + (eq_attr "type" "fmul") + "p5600_fpu_long, p5600_fpu_apu") + +;; fdiv, fsqrt +(define_insn_reservation "p5600_fpu_div" 17 + (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt") + "p5600_fpu_long, p5600_fpu_apu*17") + +;; fcvt +(define_insn_reservation "p5600_fpu_fcvt" 4 + (eq_attr "type" "fcvt") + "p5600_fpu_long, p5600_fpu_apu") + +;; mtc +(define_insn_reservation "p5600_fpu_fmtc" 7 + (eq_attr "type" "mtc") + "p5600_fpu_short, p5600_fpu_store") + +;; mfc +(define_insn_reservation "p5600_fpu_fmfc" 4 + (eq_attr "type" "mfc") + "p5600_fpu_short, p5600_fpu_store") + +;; madd/msub feeding into the add source +;; madd.fmt dst, x, y, z -> madd.fmt a, dst, b, c 5 cycles +(define_bypass 5 "p5600_fpu_fmadd" "p5600_fpu_fmadd" "mips_fmadd_bypass") + +;; +;; Integer pipe +;; + +;; AND +(define_insn_reservation "p5600_int_and" 1 + (eq_attr "move_type" "logical") + "p5600_alq_alu") + +;; LUI +(define_insn_reservation "p5600_int_lui" 1 + (eq_attr "move_type" "const") + "p5600_alq_alu") + +;; Load LB, LBU, LH, LHU, LQ, LW, LW_I2F, LWXS +(define_insn_reservation "p5600_int_load" 4 + (eq_attr "move_type" "load") + "p5600_agq_ldsta") + +;; store +(define_insn_reservation "p5600_int_store" 3 + (eq_attr "move_type" "store") + "p5600_agq_ldsta") + +;; ANDI, SLL, SRL, SEB, SEH +(define_insn_reservation "p5600_int_arith_1" 1 + (eq_attr "move_type" "andi,sll0,signext") + "p5600_agq_al2 | p5600_alq_alu") + +;; ADDI, ADDIU, ORI, XORI, ADD, ADDU +(define_insn_reservation "p5600_int_arith_2" 1 + (eq_attr "alu_type" "add,or,xor") + "p5600_agq_al2 | p5600_alq_alu") + +;; NOR, SUB +(define_insn_reservation "p5600_int_arith_3" 1 + (eq_attr "alu_type" "nor,sub") + "p5600_alq_alu") + +;; SRL, SRA, ROTR, SLT, SLLV, SRLV +(define_insn_reservation "p5600_int_arith_4" 1 + (eq_attr "type" "shift,slt,move") + "p5600_agq_al2 | p5600_alq_alu") + +;; NOP +(define_insn_reservation "p5600_int_nop" 0 + (eq_attr "type" "nop") + "p5600_agq_al2") + +;; CLO CLZ +(define_insn_reservation "p5600_int_countbits" 1 + (eq_attr "type" "clz") + "p5600_agq_al2") + +;; Conditional moves +(define_insn_reservation "p5600_int_condmove" 1 + (eq_attr "type" "condmove") + "p5600_agq_al2") + +;; MADD MSUB +(define_insn_reservation "p5600_dsp_mac" 5 + (eq_attr "type" "imadd") + "p5600_agq_al2") + +;; MFHI/LO +(define_insn_reservation "p5600_dsp_mfhilo" 1 + (eq_attr "type" "mfhi,mflo") + "p5600_agq_al2") + +;; MTHI/LO +(define_insn_reservation "p5600_dsp_mthilo" 5 + (eq_attr "type" "mthi,mtlo") + "p5600_agq_al2") + +;; MULT MULTU MUL +(define_insn_reservation "p5600_dsp_mult" 5 + (eq_attr "type" "imul3,imul") + "p5600_agq_al2") + +;; branch and jump +(define_insn_reservation "p5600_int_branch" 1 + (eq_attr "type" "branch,jump") + "p5600_agq_ctistd") + +;; prefetch +(define_insn_reservation "p5600_int_prefetch" 3 + (eq_attr "type" "prefetch,prefetchx") + "p5600_agq_ldsta") + +;; devide +(define_insn_reservation "p5600_int_div" 8 + (eq_attr "type" "idiv") + "p5600_agq_al2+p5600_gpdiv*8") + +;; arith +(define_insn_reservation "p5600_int_arith_5" 2 + (eq_attr "type" "arith") + "p5600_agq_al2") + +;; call +(define_insn_reservation "p5600_int_call" 2 + (eq_attr "jal" "indirect,direct") + "p5600_agq_ctistd") Index: gcc/config/mips/mips-cpus.def =================================================================== --- gcc/config/mips/mips-cpus.def (revision 211230) +++ gcc/config/mips/mips-cpus.def (working copy) @@ -49,7 +49,7 @@ for this yet, so in the short term we will use the same processor entry as mips32r2. */ MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34, PTF_AVOID_BRANCHLIKELY) -MIPS_CPU ("mips32r5", PROCESSOR_74KF2_1, 36, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY) MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY) /* ??? For now just tune the generic MIPS64r2 and above for 5KC as well. */ MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY) @@ -145,6 +145,9 @@ MIPS_CPU ("1004kf", PROCESSOR_24KF2_1, 33, 0) MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, 33, 0) +/* MIPS32 Release 5 processors. */ +MIPS_CPU ("p5600", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY) + /* MIPS64 processors. */ MIPS_CPU ("5kc", PROCESSOR_5KC, 64, 0) MIPS_CPU ("5kf", PROCESSOR_5KF, 64, 0) Index: gcc/config/mips/mips-protos.h =================================================================== --- gcc/config/mips/mips-protos.h (revision 211230) +++ gcc/config/mips/mips-protos.h (working copy) @@ -315,6 +315,7 @@ extern bool mask_low_and_shift_p (enum machine_mode, rtx, rtx, int); extern int mask_low_and_shift_len (enum machine_mode, rtx, rtx); extern bool and_operands_ok (enum machine_mode, rtx, rtx); +extern bool mips_fmadd_bypass (rtx, rtx); union mips_gen_fn_ptrs { Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c (revision 211230) +++ gcc/config/mips/mips.c (working copy) @@ -1180,6 +1180,19 @@ COSTS_N_INSNS (68), /* int_div_di */ 1, /* branch_cost */ 4 /* memory_latency */ + }, + { /* P5600 */ + COSTS_N_INSNS (4), /* fp_add */ + COSTS_N_INSNS (5), /* fp_mult_sf */ + COSTS_N_INSNS (5), /* fp_mult_df */ + COSTS_N_INSNS (17), /* fp_div_sf */ + COSTS_N_INSNS (17), /* fp_div_df */ + COSTS_N_INSNS (5), /* int_mult_si */ + COSTS_N_INSNS (5), /* int_mult_di */ + COSTS_N_INSNS (8), /* int_div_si */ + COSTS_N_INSNS (8), /* int_div_di */ + 2, /* branch_cost */ + 10 /* memory_latency */ } }; @@ -13073,6 +13086,31 @@ return s; } +/* Return true if destination of IN_INSN is used as add source in + OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example: + madd.s dst, x, y, z + madd.s a, dst, b, c */ + +bool +mips_fmadd_bypass (rtx out_insn, rtx in_insn) +{ + int dst_reg, src_reg; + + gcc_assert (get_attr_type (in_insn) == TYPE_FMADD); + gcc_assert (get_attr_type (out_insn) == TYPE_FMADD); + + extract_insn (in_insn); + dst_reg = REG_P (recog_data.operand[0]); + + extract_insn (out_insn); + src_reg = REG_P (recog_data.operand[1]); + + if (dst_reg == src_reg) + return true; + + return false; +} + /* Return true if IN_INSN is a multiply-add or multiply-subtract instruction and if OUT_INSN assigns to the accumulator operand. */ @@ -13208,6 +13246,7 @@ case PROCESSOR_LOONGSON_2E: case PROCESSOR_LOONGSON_2F: case PROCESSOR_LOONGSON_3A: + case PROCESSOR_P5600: return 4; case PROCESSOR_XLP: @@ -13343,6 +13382,9 @@ if (TUNE_OCTEON) return 2; + if (TUNE_P5600) + return 4; + return 0; } Index: gcc/config/mips/mips.h =================================================================== --- gcc/config/mips/mips.h (revision 211230) +++ gcc/config/mips/mips.h (working copy) @@ -264,6 +264,7 @@ || mips_tune == PROCESSOR_OCTEON2) #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ || mips_tune == PROCESSOR_SB1A) +#define TUNE_P5600 (mips_tune == PROCESSOR_P5600) /* Whether vector modes and intrinsics for ST Microelectronics Loongson-2E/2F processors should be enabled. In o32 pairs of @@ -306,7 +307,8 @@ #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ || TUNE_MIPS4120 \ || TUNE_MIPS4130 \ - || TUNE_24K) + || TUNE_24K \ + || TUNE_P5600) #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) @@ -724,7 +726,7 @@ %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \ %{march=mips32r3: -mips32r3} \ - %{march=mips32r5: -mips32r5} \ + %{march=mips32r5|march=p5600: -mips32r5} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \