From patchwork Tue Jul 21 14:56:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bennett X-Patchwork-Id: 498264 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1D89E140D31 for ; Wed, 22 Jul 2015 00:56:36 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=ADdmk9pJ; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=UrG ESUQOIBwx7Swghm6FrviquJVWRQBFCdZWy5Zth/h3FQ1GAeyFX854d4gNNV4lGrQ 8bw9j4jrY56fws/ZkJI1tNVBsJxOIbLiRKb45+l7/3zh0Fhi9WBgGhDvgKM3BnFF U9ZFmTYXz1DdSlaKkcgLTosZcRhsHICw0LBTiet0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=h9EDLkykj CxzzUUtWfaNuiHD92A=; b=ADdmk9pJcZoUidRllIcdFE1dJuh1+e9OefkpAeGBR NPsbBzSr2kYcH9aBbB4AohPoDxUZrXsevfHs9Yi5w07sk1fVBTWm0Zn5Rg8bTAct AvqGnZChIzWajTyPtpzjs4ah00SWK5n1rFoNs37zlQ69N4VEba9Jks5kCx+9n/C4 Pk= Received: (qmail 72872 invoked by alias); 21 Jul 2015 14:56:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 72862 invoked by uid 89); 21 Jul 2015 14:56:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 Jul 2015 14:56:27 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 598CB571AFD9A; Tue, 21 Jul 2015 15:56:22 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 21 Jul 2015 15:56:25 +0100 Received: from LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9]) by LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9%17]) with mapi id 14.03.0210.002; Tue, 21 Jul 2015 15:56:24 +0100 From: Andrew Bennett To: "gcc-patches@gcc.gnu.org" CC: Matthew Fortune , "Moore, Catherine (Catherine_Moore@mentor.com)" Subject: [PATCH] MIPS: Add the lo register to the clobber list in the madd-8.c and msub-8.c testcases Date: Tue, 21 Jul 2015 14:56:23 +0000 Message-ID: <0DA23CC379F5F945ACB41CF394B98277210F9AA5@LEMAIL01.le.imgtec.org> MIME-Version: 1.0 X-IsSubscribed: yes Hi, The lo register is not listed in the clobber list in the inline asm statement for the madd-8.c and msub-8.c testcases. This means that when building for the n64 ABI GCC is free to use the lo register instead of the stack when saving/restoring the clobbered registers. Then then means that it decides to use the msub/madd instruction to perform the "x - y * z" operation rather than using mul; addu/subu which the test is looking for. The following patch therefore adds the lo register to the clobber list for the madd-8.c and msub-8.c testcases. The patch has been tested on the mti/img elf/linux-gnu toolchains, and there have been no new regressions. The patch and ChangeLog are below. Ok to commit? Many thanks, Andrew testsuite/ gcc.target/mips/madd-8.c: Add lo register to clobber list. gcc.target/mips/msub-8.c: Ditto diff --git a/gcc/testsuite/gcc.target/mips/madd-8.c b/gcc/testsuite/gcc.target/mips/madd-8.c index 794a6ff..56c1947 100644 --- a/gcc/testsuite/gcc.target/mips/madd-8.c +++ b/gcc/testsuite/gcc.target/mips/madd-8.c @@ -11,6 +11,6 @@ f2 (int x, int y, int z) asm volatile ("" ::: "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", - "$31"); + "$31", "lo"); return x * y + z; } diff --git a/gcc/testsuite/gcc.target/mips/msub-8.c b/gcc/testsuite/gcc.target/mips/msub-8.c index a66307f..b0f1523 100644 --- a/gcc/testsuite/gcc.target/mips/msub-8.c +++ b/gcc/testsuite/gcc.target/mips/msub-8.c @@ -11,6 +11,6 @@ f2 (int x, int y, int z) asm volatile ("" ::: "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", - "$31"); + "$31", "lo"); return x - y * z; }