From patchwork Fri Jul 3 23:50:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Bennett X-Patchwork-Id: 491162 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5D06214076B for ; Sat, 4 Jul 2015 09:50:37 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=I+MygaTE; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=UEI h/UIP0eYHwfarH3imDvwFbM7TzdDFbks53dPpEl5kDyv0mMPktZR6mzq7TKzn6G8 IuFlYbNqulqFNjSUy5pMVRLVCDhA0LWC98kOj1NXAUP7kppAa+xUxCT4oUcDUp4M 5DqWpBryZKv8BBARQsRTjOjucCwOk3Iqzo8ynOPk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=fXlfFUKDw cRFbHZ2zY6tgyNC9GI=; b=I+MygaTECTnkocwdx1lRuAsOfarwWmVUCzYYq9sX9 UXpcwkci1/BBh67nsSMPqQsTabgcfPSlyqU1xDTIVdYyCGFMiHxf7hNpmPjisIhu yea3DN9AjhM85OeWTo+4vZMuvoNWBz7gR/210p0VpGEe05usS+OAsmJS7Mb7p1RN Pk= Received: (qmail 124391 invoked by alias); 3 Jul 2015 23:50:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 124377 invoked by uid 89); 3 Jul 2015 23:50:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 03 Jul 2015 23:50:27 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id D9F03DC876029 for ; Sat, 4 Jul 2015 00:50:19 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Sat, 4 Jul 2015 00:50:23 +0100 Received: from LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9]) by LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9%17]) with mapi id 14.03.0210.002; Sat, 4 Jul 2015 00:50:23 +0100 From: Andrew Bennett To: "gcc-patches@gcc.gnu.org" CC: Matthew Fortune Subject: [PATCH] MIPS: fix failing branch range checks for micromips Date: Fri, 3 Jul 2015 23:50:21 +0000 Message-ID: <0DA23CC379F5F945ACB41CF394B98277210EDC9C@LEMAIL01.le.imgtec.org> MIME-Version: 1.0 X-IsSubscribed: yes Hi, The current branch range tests assume that the MIPS branch instructions have a 16 bit branch offset which is shifted by 2.  Unfortunately for microMIPS this offset is shifted by 1 which reduces the branch range and is causing the branch-[2,4,6,10,12].c tests to fail.    The following patch fixes this issue by firstly adding a new macro to branch-helper.h which outputs the correct number of nops to describe the maximum positive range of a 16 bit micromips branch offset (assuming the branch instruction has a delay slot). Secondly it breaks-up the branch-[2,4,6,10,12].c files into mips tests (which have -mno-micromips added to them) and micromips tests (which use the new macro). I have tested this on the mips-mti-elf target using mips32r2/{-mno-micromips/-mmicromips} test options and there are no new regressions.   There is a follow-up patch that I will be working on that will correctly update the other branch tests to correctly test out of range branch behaviour for micromips.  Currently these are passing because the mips branch range offset is large enough.  These offsets will need to be reduced for micromips to verify the compiler is calculating branch ranges correctly. The ChangeLog and patch are below. Ok to commit? Many thanks, Andrew testsuite/ * gcc.target/mips/branch-2.c: Add -mno-micromips to dg-options. * gcc.target/mips/branch-4.c: Ditto. * gcc.target/mips/branch-6.c: Ditto. * gcc.target/mips/branch-8.c: Ditto. * gcc.target/mips/branch-10.c: Ditto. * gcc.target/mips/branch-12.c: Ditto. * gcc.target/mips/branch-umips-2.c: New file. * gcc.target/mips/branch-umips-4.c: New file. * gcc.target/mips/branch-umips-6.c: New file. * gcc.target/mips/branch-umips-8.c: New file. * gcc.target/mips/branch-umips-10.c: New file. * gcc.target/mips/branch-umips-12.c: New file. * gcc.target/mips/branch-helper.h (OCCUPY_0xfffc): New define. diff --git a/gcc/testsuite/gcc.target/mips/branch-10.c b/gcc/testsuite/gcc.target/mips/branch-10.c index e2b1b5f..00569b0 100644 --- a/gcc/testsuite/gcc.target/mips/branch-10.c +++ b/gcc/testsuite/gcc.target/mips/branch-10.c @@ -1,4 +1,4 @@ -/* { dg-options "-mshared -mabi=n32" } */ +/* { dg-options "-mshared -mabi=n32 -mno-micromips" } */ /* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-12.c b/gcc/testsuite/gcc.target/mips/branch-12.c index 4aef160..7d7580b 100644 --- a/gcc/testsuite/gcc.target/mips/branch-12.c +++ b/gcc/testsuite/gcc.target/mips/branch-12.c @@ -1,4 +1,4 @@ -/* { dg-options "-mshared -mabi=64" } */ +/* { dg-options "-mshared -mabi=64 -mno-micromips" } */ /* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-2.c b/gcc/testsuite/gcc.target/mips/branch-2.c index 6409c4c..241e885 100644 --- a/gcc/testsuite/gcc.target/mips/branch-2.c +++ b/gcc/testsuite/gcc.target/mips/branch-2.c @@ -1,4 +1,4 @@ -/* { dg-options "-mshared -mabi=32" } */ +/* { dg-options "-mshared -mabi=32 -mno-micromips" } */ /* { dg-final { scan-assembler-not "(\\\$25|\\\$28|cpload)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ /* { dg-final { scan-assembler-not "\\.cprestore" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-4.c b/gcc/testsuite/gcc.target/mips/branch-4.c index 31e4909..923e6d4 100644 --- a/gcc/testsuite/gcc.target/mips/branch-4.c +++ b/gcc/testsuite/gcc.target/mips/branch-4.c @@ -1,4 +1,4 @@ -/* { dg-options "-mshared -mabi=n32" } */ +/* { dg-options "-mshared -mabi=n32 -mno-micromips" } */ /* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-6.c b/gcc/testsuite/gcc.target/mips/branch-6.c index 77e0340..2c75ab1 100644 --- a/gcc/testsuite/gcc.target/mips/branch-6.c +++ b/gcc/testsuite/gcc.target/mips/branch-6.c @@ -1,4 +1,4 @@ -/* { dg-options "-mshared -mabi=64" } */ +/* { dg-options "-mshared -mabi=64 -mno-micromips" } */ /* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-8.c b/gcc/testsuite/gcc.target/mips/branch-8.c index ba5f954..85df6b8 100644 --- a/gcc/testsuite/gcc.target/mips/branch-8.c +++ b/gcc/testsuite/gcc.target/mips/branch-8.c @@ -1,4 +1,4 @@ -/* { dg-options "-mshared -mabi=32" } */ +/* { dg-options "-mshared -mabi=32 -mno-micromips" } */ /* { dg-final { scan-assembler-not "(\\\$28|cpload|cprestore)" } } */ /* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/branch-helper.h b/gcc/testsuite/gcc.target/mips/branch-helper.h index 85399be..bc4a31f 100644 --- a/gcc/testsuite/gcc.target/mips/branch-helper.h +++ b/gcc/testsuite/gcc.target/mips/branch-helper.h @@ -33,5 +33,23 @@ D2 ("nop") "\n\t" \ D1 ("nop")) +/* Emit something that is 0xfffc bytes long, which is the largest + permissible range for micromips forward branches when branches + have delay slots. */ +#define OCCUPY_0xfffc \ + asm (D13 ("nop32") "\n\t" \ + D12 ("nop32") "\n\t" \ + D11 ("nop32") "\n\t" \ + D10 ("nop32") "\n\t" \ + D9 ("nop32") "\n\t" \ + D8 ("nop32") "\n\t" \ + D7 ("nop32") "\n\t" \ + D6 ("nop32") "\n\t" \ + D5 ("nop32") "\n\t" \ + D4 ("nop32") "\n\t" \ + D3 ("nop32") "\n\t" \ + D2 ("nop32") "\n\t" \ + D1 ("nop32") "\n\t" \ + D0 ("nop32")) /* Likewise emit something that is 0x1fffc bytes long. */ #define OCCUPY_0x1fffc do { asm ("nop"); OCCUPY_0x1fff8; } while (0) diff --git a/gcc/testsuite/gcc.target/mips/branch-umips-10.c b/gcc/testsuite/gcc.target/mips/branch-umips-10.c new file mode 100644 index 0000000..e84b462 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/branch-umips-10.c @@ -0,0 +1,13 @@ +/* { dg-options "-mshared -mabi=n32 -mmicromips" } */ +/* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */ +/* { dg-final { scan-assembler-not "\tjrc?\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (int (*bar) (void), int *x) +{ + *x = bar (); + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0xfffc; +} diff --git a/gcc/testsuite/gcc.target/mips/branch-umips-12.c b/gcc/testsuite/gcc.target/mips/branch-umips-12.c new file mode 100644 index 0000000..6704aad --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/branch-umips-12.c @@ -0,0 +1,13 @@ +/* { dg-options "-mshared -mabi=64 -mmicromips" } */ +/* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */ +/* { dg-final { scan-assembler-not "\tjrc?\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (int (*bar) (void), int *x) +{ + *x = bar (); + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0xfffc; +} diff --git a/gcc/testsuite/gcc.target/mips/branch-umips-2.c b/gcc/testsuite/gcc.target/mips/branch-umips-2.c new file mode 100644 index 0000000..d124f91 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/branch-umips-2.c @@ -0,0 +1,13 @@ +/* { dg-options "-mshared -mabi=32 -mmicromips" } */ +/* { dg-final { scan-assembler-not "(\\\$25|\\\$28|cpload)" } } */ +/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\\.cprestore" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0xfffc; +} diff --git a/gcc/testsuite/gcc.target/mips/branch-umips-4.c b/gcc/testsuite/gcc.target/mips/branch-umips-4.c new file mode 100644 index 0000000..294805a --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/branch-umips-4.c @@ -0,0 +1,12 @@ +/* { dg-options "-mshared -mabi=n32 -mmicromips" } */ +/* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */ +/* { dg-final { scan-assembler-not "\tjrc?\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0xfffc; +} diff --git a/gcc/testsuite/gcc.target/mips/branch-umips-6.c b/gcc/testsuite/gcc.target/mips/branch-umips-6.c new file mode 100644 index 0000000..ab02e88 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/branch-umips-6.c @@ -0,0 +1,12 @@ +/* { dg-options "-mshared -mabi=64 -mmicromips" } */ +/* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */ +/* { dg-final { scan-assembler-not "\tjrc?\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (volatile int *x) +{ + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0xfffc; +} diff --git a/gcc/testsuite/gcc.target/mips/branch-umips-8.c b/gcc/testsuite/gcc.target/mips/branch-umips-8.c new file mode 100644 index 0000000..5050669 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/branch-umips-8.c @@ -0,0 +1,13 @@ +/* { dg-options "-mshared -mabi=32 -mmicromips" } */ +/* { dg-final { scan-assembler-not "(\\\$28|cpload|cprestore)" } } */ +/* { dg-final { scan-assembler-not "\tjrc?\t\\\$1\n" } } */ + +#include "branch-helper.h" + +NOMIPS16 void +foo (int (*bar) (void), int *x) +{ + *x = bar (); + if (__builtin_expect (*x == 0, 1)) + OCCUPY_0xfffc; +}