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(d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1ABBIWfg58327376 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 11 Nov 2021 11:18:32 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A6BE54C064; Thu, 11 Nov 2021 11:25:13 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DB9934C040; Thu, 11 Nov 2021 11:25:12 +0000 (GMT) Received: from trout.aus.stglabs.ibm.com (unknown [9.40.194.100]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 11 Nov 2021 11:25:12 +0000 (GMT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 06/15] visium: Fix non-robust split condition in define_insn_and_split Date: Thu, 11 Nov 2021 05:24:50 -0600 Message-Id: <081199b9c29ee164cba277a3b9ac2623cf630fc2.1636621345.git.linkw@linux.ibm.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: AMhgins1i04oHj-AUSBGOKIic2D3k977 X-Proofpoint-ORIG-GUID: AMhgins1i04oHj-AUSBGOKIic2D3k977 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-11_03,2021-11-08_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1011 mlxscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2111110066 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Kewen Lin via Gcc-patches From: "Kewen.Lin" Reply-To: Kewen Lin Cc: ebotcazou@adacore.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch is to fix some non-robust split conditions in some define_insn_and_splits, to make each of them applied on top of the corresponding condition for define_insn part, otherwise the splitting could perform unexpectedly. gcc/ChangeLog: * config/visium/visium.md (*add3_insn, *addsi3_insn, *addi3_insn, *sub3_insn, *subsi3_insn, *subdi3_insn, *neg2_insn, *negdi2_insn, *and3_insn, *ior3_insn, *xor3_insn, *one_cmpl2_insn, *ashl3_insn, *ashr3_insn, *lshr3_insn, *trunchiqi2_insn, *truncsihi2_insn, *truncdisi2_insn, *extendqihi2_insn, *extendqisi2_insn, *extendhisi2_insn, *extendsidi2_insn, *zero_extendqihi2_insn, *zero_extendqisi2_insn, *zero_extendsidi2_insn): Fix split condition. --- gcc/config/visium/visium.md | 50 ++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/gcc/config/visium/visium.md b/gcc/config/visium/visium.md index 83ccf088124..ca2234bf253 100644 --- a/gcc/config/visium/visium.md +++ b/gcc/config/visium/visium.md @@ -792,7 +792,7 @@ (define_insn_and_split "*add3_insn" (match_operand:QHI 2 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, mode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (plus:QHI (match_dup 1) (match_dup 2))) (clobber (reg:CC R_FLAGS))])] @@ -850,7 +850,7 @@ (define_insn_and_split "*addsi3_insn" (match_operand:SI 2 "add_operand" " L,r,J")))] "ok_for_simple_arith_logic_operands (operands, SImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) (clobber (reg:CC R_FLAGS))])] @@ -912,7 +912,7 @@ (define_insn_and_split "*addi3_insn" (match_operand:DI 2 "add_operand" " L,J, r")))] "ok_for_simple_arith_logic_operands (operands, DImode)" "#" - "reload_completed" + "&& reload_completed" [(const_int 0)] { visium_split_double_add (PLUS, operands[0], operands[1], operands[2]); @@ -1007,7 +1007,7 @@ (define_insn_and_split "*sub3_insn" (match_operand:QHI 2 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, mode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (minus:QHI (match_dup 1) (match_dup 2))) (clobber (reg:CC R_FLAGS))])] @@ -1064,7 +1064,7 @@ (define_insn_and_split "*subsi3_insn" (match_operand:SI 2 "add_operand" " L,r, J")))] "ok_for_simple_arith_logic_operands (operands, SImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2))) (clobber (reg:CC R_FLAGS))])] @@ -1125,7 +1125,7 @@ (define_insn_and_split "*subdi3_insn" (match_operand:DI 2 "add_operand" " L,J, r")))] "ok_for_simple_arith_logic_operands (operands, DImode)" "#" - "reload_completed" + "&& reload_completed" [(const_int 0)] { visium_split_double_add (MINUS, operands[0], operands[1], operands[2]); @@ -1209,7 +1209,7 @@ (define_insn_and_split "*neg2_insn" (neg:I (match_operand:I 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, mode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (neg:I (match_dup 1))) (clobber (reg:CC R_FLAGS))])] "" @@ -1253,7 +1253,7 @@ (define_insn_and_split "*negdi2_insn" (neg:DI (match_operand:DI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, DImode)" "#" - "reload_completed" + "&& reload_completed" [(const_int 0)] { visium_split_double_add (MINUS, operands[0], const0_rtx, operands[1]); @@ -1415,7 +1415,7 @@ (define_insn_and_split "*and3_insn" (match_operand:I 2 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, mode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (and:I (match_dup 1) (match_dup 2))) (clobber (reg:CC R_FLAGS))])] @@ -1453,7 +1453,7 @@ (define_insn_and_split "*ior3_insn" (match_operand:I 2 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, mode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (ior:I (match_dup 1) (match_dup 2))) (clobber (reg:CC R_FLAGS))])] @@ -1491,7 +1491,7 @@ (define_insn_and_split "*xor3_insn" (match_operand:I 2 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, mode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (xor:I (match_dup 1) (match_dup 2))) (clobber (reg:CC R_FLAGS))])] @@ -1527,7 +1527,7 @@ (define_insn_and_split "*one_cmpl2_insn" (not:I (match_operand:I 1 "reg_or_0_operand" "rO")))] "ok_for_simple_arith_logic_operands (operands, mode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (not:I (match_dup 1))) (clobber (reg:CC R_FLAGS))])] "" @@ -1563,7 +1563,7 @@ (define_insn_and_split "*ashl3_insn" (match_operand:QI 2 "reg_or_shift_operand" "r,K")))] "ok_for_simple_arith_logic_operands (operands, mode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (ashift:I (match_dup 1) (match_dup 2))) (clobber (reg:CC R_FLAGS))])] @@ -1622,7 +1622,7 @@ (define_insn_and_split "*ashr3_insn" (match_operand:QI 2 "reg_or_shift_operand" "r,K")))] "ok_for_simple_arith_logic_operands (operands, mode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (ashiftrt:I (match_dup 1) (match_dup 2))) (clobber (reg:CC R_FLAGS))])] @@ -1683,7 +1683,7 @@ (define_insn_and_split "*lshr3_insn" (match_operand:QI 2 "reg_or_shift_operand" "r,K")))] "ok_for_simple_arith_logic_operands (operands, mode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (lshiftrt:I (match_dup 1) (match_dup 2))) (clobber (reg:CC R_FLAGS))])] @@ -1740,7 +1740,7 @@ (define_insn_and_split "*trunchiqi2_insn" (truncate:QI (match_operand:HI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, QImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (truncate:QI (match_dup 1))) (clobber (reg:CC R_FLAGS))])] "" @@ -1764,7 +1764,7 @@ (define_insn_and_split "*truncsihi2_insn" (truncate:HI (match_operand:SI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, HImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (truncate:HI (match_dup 1))) (clobber (reg:CC R_FLAGS))])] "" @@ -1788,7 +1788,7 @@ (define_insn_and_split "*truncdisi2_insn" (truncate:SI (match_operand:DI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, SImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (truncate:SI (match_dup 1))) (clobber (reg:CC R_FLAGS))])] "" @@ -1822,7 +1822,7 @@ (define_insn_and_split "*extendqihi2_insn" (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, HImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (sign_extend:HI (match_dup 1))) (clobber (reg:CC R_FLAGS))])] "" @@ -1846,7 +1846,7 @@ (define_insn_and_split "*extendqisi2_insn" (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, SImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (sign_extend:SI (match_dup 1))) (clobber (reg:CC R_FLAGS))])] "" @@ -1870,7 +1870,7 @@ (define_insn_and_split "*extendhisi2_insn" (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, SImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:HI 1 "register_operand" ""))) (clobber (reg:CC R_FLAGS))])] @@ -1895,7 +1895,7 @@ (define_insn_and_split "*extendsidi2_insn" (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, DImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 3) (match_dup 1)) (clobber (reg:CC R_FLAGS))]) (parallel [(set (match_dup 2) @@ -1931,7 +1931,7 @@ (define_insn_and_split "*zero_extendqihi2_insn" (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, HImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (ashift:HI (match_dup 2) (const_int 8))) (clobber (reg:CC R_FLAGS))]) @@ -1953,7 +1953,7 @@ (define_insn_and_split "*zero_extendqisi2_insn" (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, SImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24))) (clobber (reg:CC R_FLAGS))]) @@ -1982,7 +1982,7 @@ (define_insn_and_split "*zero_extendsidi2_insn" (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] "ok_for_simple_arith_logic_operands (operands, DImode)" "#" - "reload_completed" + "&& reload_completed" [(parallel [(set (match_dup 3) (match_dup 1)) (clobber (reg:CC R_FLAGS))]) (set (match_dup 2) (const_int 0))]