From patchwork Wed Jun 26 12:20:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1952575 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4W8LQC4FNhz20X1 for ; Wed, 26 Jun 2024 22:20:51 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D9C43387100A for ; Wed, 26 Jun 2024 12:20:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id AAAC8386D60C for ; Wed, 26 Jun 2024 12:20:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AAAC8386D60C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AAAC8386D60C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719404429; cv=none; b=MHoCPbn/fyqbNZrCSSTC4rNcFV4SkpjELrHkJ+P8caKq583PBBPG1bN3gib7J1zrjN8pCiRtAMLGX8kz7qtw1oJYzi2o9PjpAlIN96D49RCYaZ1L4qhwIiihOhSiFWmsQ+gXydXjk3tnHrLlOZJJCzfO+WO4hqzY1qSrKUg8j8c= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719404429; c=relaxed/simple; bh=w0zsIbgY+2kaKgtb1AAmEWbHlhKxgfvsVxxHXqZiGCo=; h=Message-ID:Date:MIME-Version:To:From:Subject; b=CEag/J06cEGoOjW7xMLSd0ORwqN/fR6/LRMbVOlqj14+IC4GHlS57DIDYSNEu2Q5uUm0klOa85ykXTV9Z6xjDIJrt72NXv84PHvWj9gfPmDy99WeNUlFVbQIJtk5zLUvn7YWY6t358VLZg3mumUWgMX5h5I790bn5R65psd2oR4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3102E339 for ; Wed, 26 Jun 2024 05:20:52 -0700 (PDT) Received: from [10.57.80.234] (unknown [10.57.80.234]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0C57A3F73B for ; Wed, 26 Jun 2024 05:20:26 -0700 (PDT) Message-ID: <03e38220-b096-40c1-8007-1bfac5495c2f@arm.com> Date: Wed, 26 Jun 2024 13:20:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "gcc-patches@gcc.gnu.org" From: "Andre Vieira (lists)" Subject: mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611] X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch fixes the backend pattern that was printing the wrong input scalar register pair when inserting into lane 1. Added a new test to force float-abi=hard so we can use scan-assembler to check correct codegen. Regression tested arm-none-eabi with -march=armv8.1-m.main+mve/-mfloat-abi=hard/-mfpu=auto gcc/ChangeLog: PR target/115611 * config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of input scalar register pair when lane = 1. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test. diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 4b4d6298ffb1899dc089eb52b03500e6e6236c31..706a45c7d6652677f3ec993a77646e3845eb8f8d 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -6505,7 +6505,7 @@ (define_insn "mve_vec_setv2di_internal" if (elt == 0) return "vmov\t%e0, %Q1, %R1"; else - return "vmov\t%f0, %J1, %K1"; + return "vmov\t%f0, %Q1, %R1"; } [(set_attr "type" "mve_move")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c new file mode 100644 index 0000000000000000000000000000000000000000..5aa3bc9a76a06d7151ff6a844807afe666bbeacb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c @@ -0,0 +1,63 @@ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-require-effective-target arm_hard_ok } */ +/* { dg-additional-options "-mfloat-abi=hard -O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_mve.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* +**fn1: +** vmov d0, r0, r1 +** bx lr +*/ +uint64x2_t +fn1 (uint64_t a, uint64x2_t b) +{ + return vsetq_lane_u64 (a, b, 0); +} + +/* +**fn2: +** vmov d1, r0, r1 +** bx lr +*/ +uint64x2_t +fn2 (uint64_t a, uint64x2_t b) +{ + return vsetq_lane_u64 (a, b, 1); +} + +/* +**fn3: +** vmov d0, r0, r1 +** bx lr +*/ +int64x2_t +fn3 (int64_t a, int64x2_t b) +{ + return vsetq_lane_s64 (a, b, 0); +} + +/* +**fn4: +** vmov d1, r0, r1 +** bx lr +*/ +int64x2_t +fn4 (int64_t a, int64x2_t b) +{ + return vsetq_lane_s64 (a, b, 1); +} + + +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ +