From patchwork Tue Jul 11 19:07:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 1806497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nextmovesoftware.com header.i=@nextmovesoftware.com header.a=rsa-sha256 header.s=default header.b=NxKq3dCC; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R0r6T0ZBCz20ZZ for ; Wed, 12 Jul 2023 05:10:07 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 42835385C6E4 for ; Tue, 11 Jul 2023 19:10:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 824C1385734D for ; Tue, 11 Jul 2023 19:07:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 824C1385734D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=PFXZJp+LCkTRnYvA8UQxZv4eyOqud6IW2lV1dFEo6uc=; b=NxKq3dCC8rYAeHXVfzQNVfRwCi QTwhuvunCeED1M53nx5UhJgDcwIv9awD9ZTwshz/fLCM297dgSLe7LA9+/y0oMI8Pby5HJtRmmCG5 zXkqBhr5uS4G0DBZE/NZ8GeoGxjPYohhJgkj9JMxlTeo/tJqrt9YlXi3YM5q5Zp+vlX0rUvT/n0kf zjjd8HYUxHELBf9QIlmgInSV3xn93LpjbHcFrJEqq6RSDD/uxZE1hEyipFTu2ifYH0mWw1YupkyyN +DEi3mSL3uaBrFIVhT9BNAGHGijbYP1Ldt2yNS1BGqvbVzdAnJD+oVG0oOcb7VDaZwJceN0cGX9K3 9GxZvDgA==; Received: from host86-161-68-50.range86-161.btcentralplus.com ([86.161.68.50]:50552 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1qJIiG-0002Cw-1I; Tue, 11 Jul 2023 15:07:52 -0400 From: "Roger Sayle" To: Cc: "'Uros Bizjak'" Subject: [x86 PATCH] PR target/110598: Fix rega = 0; rega ^= rega regression. Date: Tue, 11 Jul 2023 20:07:50 +0100 Message-ID: <028501d9b42a$fe59bba0$fb0d32e0$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: Adm0KQcoR7KVNAEIT0u7P6wUfQ31kw== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch fixes the regression PR target/110598 caused by my recent addition of a peephole2. The intention of that optimization was to simplify zeroing a register, followed by an IOR, XOR or PLUS operation on it into a move, or as described in the comment: ;; Peephole2 rega = 0; rega op= regb into rega = regb. The issue is that I'd failed to consider the (rare and unusual) case, where regb is rega, where the transformation leads to the incorrect "rega = rega", when it should be "rega = 0". The minimal fix is to add a !reg_mentioned_p check to the recent peephole2. In addition to resolving the regression, I've added a second peephole2 to optimize the problematic case above, which contains a false dependency and is therefore tricky to optimize elsewhere. This is an improvement over GCC 13, for example, that generates the redundant: xorl %edx, %edx xorq %rdx, %rdx 2023-07-11 Roger Sayle gcc/ChangeLog PR target/110598 * config/i386/i386.md (peephole2): Check !reg_mentioned_p when optimizing rega = 0; rega op= regb for op in [XOR,IOR,PLUS]. (peephole2): Simplify rega = 0; rega op= rega cases. gcc/testsuite/ChangeLog PR target/110598 * gcc.target/i386/pr110598.c: New test case. Thanks in advance (and apologies for any inconvenience), Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 844deea..57c370a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -12319,9 +12319,21 @@ (any_or_plus:SWI (match_dup 0) (match_operand:SWI 1 ""))) (clobber (reg:CC FLAGS_REG))])] - "" + "!reg_mentioned_p (operands[0], operands[1])" [(set (match_dup 0) (match_dup 1))]) - + +;; Peephole2 dead instruction in rega = 0; rega op= rega. +(define_peephole2 + [(parallel [(set (match_operand:SWI 0 "general_reg_operand") + (const_int 0)) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (match_dup 0) + (any_or_plus:SWI (match_dup 0) (match_dup 0))) + (clobber (reg:CC FLAGS_REG))])] + "" + [(parallel [(set (match_dup 0) (const_int 0)) + (clobber (reg:CC FLAGS_REG))])]) + ;; Split DST = (HI<<32)|LO early to minimize register usage. (define_insn_and_split "*concat3_1" [(set (match_operand: 0 "nonimmediate_operand" "=ro,r") diff --git a/gcc/testsuite/gcc.target/i386/pr110598.c b/gcc/testsuite/gcc.target/i386/pr110598.c new file mode 100644 index 0000000..1c88031 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr110598.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +typedef unsigned long long u64; + +#define MAX_SUBTARGET_WORDS 4 + +int notequal(const void *a, const void *b) +{ + return __builtin_memcmp(a,b,MAX_SUBTARGET_WORDS*sizeof(u64)) != 0; +} +typedef struct FeatureBitset { + u64 Bits[MAX_SUBTARGET_WORDS]; +}FeatureBitset; + +__attribute__((noipa)) +_Bool is_eq_buggy (const FeatureBitset * lf, const FeatureBitset * rf) { + u64 Bits_l[MAX_SUBTARGET_WORDS]; + Bits_l[0] = lf->Bits[0]&1; + Bits_l[1] = 0; + Bits_l[2] = 0; + Bits_l[3] = 0; + u64 Bits_r[MAX_SUBTARGET_WORDS]; + Bits_r[0] = rf->Bits[0]&1; + Bits_r[1] = 0; + Bits_r[2] = 0; + Bits_r[3] = 0; + return !notequal(Bits_l, Bits_r); +} + +__attribute__((noipa)) +void bug(void) { + FeatureBitset lf, rf; + lf.Bits[0] = rf.Bits[0] = 1; + lf.Bits[1] = rf.Bits[1] = 1; + lf.Bits[2] = rf.Bits[2] = 1; + lf.Bits[3] = rf.Bits[3] = 1; + + _Bool r = is_eq_buggy (&lf, &rf); + if (!r) __builtin_trap(); +} + +__attribute__((noipa)) +int main(void) { + bug(); +}