| Message ID | 026701d80acf$2be278c0$83a76a40$@nextmovesoftware.com |
|---|---|
| State | New |
| Headers | show |
| Series | nvptx: Fix and use BI mode logic instructions (e.g. and.pred). | expand |
On 1/16/22 12:49, Roger Sayle wrote: > > This patch adds support for nvptx's BImode and.pred, or.pred and > xor.pred instructions. Technically, nvptx.md previously defined > andbi3, iorbi3 and xorbi3 instructions, but the assembly language > mnemonic output for these was incorrect (e.g. and.b1) and would be > rejected by the ptxas assembler. Thanks for catching and fixing that :) ! > The most significant part of this > patch is the new define_split which teaches the compiler to actually > use these instructions when appropriate (exposing the latent bug above). > > After https://gcc.gnu.org/pipermail/gcc-patches/2022-January/587999.html > (still awaiting review/approval), the function: > > int foo(int x, int y) { return (x==21) && (y==69); } > > when compiled with -O2 produces: > > mov.u32 %r26, %ar0; > mov.u32 %r27, %ar1; > setp.eq.u32 %r31, %r26, 21; > setp.eq.u32 %r34, %r27, 69; > selp.u32 %r37, 1, 0, %r31; > selp.u32 %r38, 1, 0, %r34; > and.b32 %value, %r37, %r38; > > with this patch we now save an extra instruction and generate: > > mov.u32 %r26, %ar0; > mov.u32 %r27, %ar1; > setp.eq.u32 %r31, %r26, 21; > setp.eq.u32 %r34, %r27, 69; > and.pred %r39, %r34, %r31; > selp.u32 %value, 1, 0, %r39; > > This patch has been tested (on top of the patch mentioned above) on > nvptx-none hosted on x86_64-pc-linux-gnu (including newlib) with a > make and make -k check with no new failures. Ok for mainline? > > LGTM, applied. Thanks, - Tom > 2022-01-16 Roger Sayle <roger@nextmovesoftware.com> > > gcc/ChangeLog > * config/nvptx/nvptx.md (any_logic): Move code iterator earlier > in machine description. > (logic): Move code attribute earlier in machine description. > (ilogic): New code attribute, like logic but "ior" for IOR. > (and<mode>3, ior<mode>3, xor<mode>3): Delete. Replace with... > (<ilogic><mode>3): New define_insn for HSDIM logic operations. > (<ilogic>bi3): New define_insn for BI mode logic operations. > (define_split): Lower logic operations from integer modes to > BI mode predicate operations. > > gcc/testsuite/ChangeLog > * gcc.target/nvptx/bool-2.c: New test case for and.pred. > * gcc.target/nvptx/bool-3.c: New test case for or.pred. > * gcc.target/nvptx/bool-4.c: New test case for xor.pred. > > > Many thanks in advance. > > Roger > -- >
diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index ce74672..0349c32 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -740,26 +740,38 @@ ;; Logical operations -(define_insn "and<mode>3" - [(set (match_operand:BHSDIM 0 "nvptx_register_operand" "=R") - (and:BHSDIM (match_operand:BHSDIM 1 "nvptx_register_operand" "R") - (match_operand:BHSDIM 2 "nvptx_nonmemory_operand" "Ri")))] - "" - "%.\\tand.b%T0\\t%0, %1, %2;") +(define_code_iterator any_logic [and ior xor]) +(define_code_attr logic [(and "and") (ior "or") (xor "xor")]) +(define_code_attr ilogic [(and "and") (ior "ior") (xor "xor")]) -(define_insn "ior<mode>3" - [(set (match_operand:BHSDIM 0 "nvptx_register_operand" "=R") - (ior:BHSDIM (match_operand:BHSDIM 1 "nvptx_register_operand" "R") - (match_operand:BHSDIM 2 "nvptx_nonmemory_operand" "Ri")))] +(define_insn "<ilogic><mode>3" + [(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R") + (any_logic:HSDIM + (match_operand:HSDIM 1 "nvptx_register_operand" "R") + (match_operand:HSDIM 2 "nvptx_nonmemory_operand" "Ri")))] "" - "%.\\tor.b%T0\\t%0, %1, %2;") + "%.\\t<logic>.b%T0\\t%0, %1, %2;") -(define_insn "xor<mode>3" - [(set (match_operand:BHSDIM 0 "nvptx_register_operand" "=R") - (xor:BHSDIM (match_operand:BHSDIM 1 "nvptx_register_operand" "R") - (match_operand:BHSDIM 2 "nvptx_nonmemory_operand" "Ri")))] +(define_insn "<ilogic>bi3" + [(set (match_operand:BI 0 "nvptx_register_operand" "=R") + (any_logic:BI (match_operand:BI 1 "nvptx_register_operand" "R") + (match_operand:BI 2 "nvptx_register_operand" "R")))] "" - "%.\\txor.b%T0\\t%0, %1, %2;") + "%.\\t<logic>.pred\\t%0, %1, %2;") + +(define_split + [(set (match_operand:HSDIM 0 "nvptx_register_operand") + (any_logic:HSDIM + (ne:HSDIM (match_operand:BI 1 "nvptx_register_operand") + (const_int 0)) + (ne:HSDIM (match_operand:BI 2 "nvptx_register_operand") + (const_int 0))))] + "can_create_pseudo_p ()" + [(set (match_dup 3) (any_logic:BI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (ne:HSDIM (match_dup 3) (const_int 0)))] +{ + operands[3] = gen_reg_rtx (BImode); +}) ;; Comparisons and branches @@ -1845,9 +1857,6 @@ } [(set_attr "atomic" "true")]) -(define_code_iterator any_logic [and ior xor]) -(define_code_attr logic [(and "and") (ior "or") (xor "xor")]) - (define_insn "atomic_fetch_<logic><mode>" [(set (match_operand:SDIM 1 "memory_operand" "+m") (unspec_volatile:SDIM diff --git a/gcc/testsuite/gcc.target/nvptx/bool-2.c b/gcc/testsuite/gcc.target/nvptx/bool-2.c new file mode 100644 index 0000000..b779248 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/bool-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int foo(int x, int y) +{ + return (x==21) && (y==69); +} + +int bar(int x, int y) +{ + return (x==21) & (y==69); +} + +/* { dg-final { scan-assembler-times "and.pred" 2 } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/bool-3.c b/gcc/testsuite/gcc.target/nvptx/bool-3.c new file mode 100644 index 0000000..ab4206a --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/bool-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int foo(int x, int y) +{ + return (x==21) || (y==69); +} + +int bar(int x, int y) +{ + return (x==21) | (y==69); +} + +/* { dg-final { scan-assembler-times "or.pred" 2 } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/bool-4.c b/gcc/testsuite/gcc.target/nvptx/bool-4.c new file mode 100644 index 0000000..b588574 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/bool-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int foo(int x, int y) +{ + return (x==21) ^ (y==69); +} + +/* { dg-final { scan-assembler "xor.pred" } } */
This patch adds support for nvptx's BImode and.pred, or.pred and xor.pred instructions. Technically, nvptx.md previously defined andbi3, iorbi3 and xorbi3 instructions, but the assembly language mnemonic output for these was incorrect (e.g. and.b1) and would be rejected by the ptxas assembler. The most significant part of this patch is the new define_split which teaches the compiler to actually use these instructions when appropriate (exposing the latent bug above). After https://gcc.gnu.org/pipermail/gcc-patches/2022-January/587999.html (still awaiting review/approval), the function: int foo(int x, int y) { return (x==21) && (y==69); } when compiled with -O2 produces: mov.u32 %r26, %ar0; mov.u32 %r27, %ar1; setp.eq.u32 %r31, %r26, 21; setp.eq.u32 %r34, %r27, 69; selp.u32 %r37, 1, 0, %r31; selp.u32 %r38, 1, 0, %r34; and.b32 %value, %r37, %r38; with this patch we now save an extra instruction and generate: mov.u32 %r26, %ar0; mov.u32 %r27, %ar1; setp.eq.u32 %r31, %r26, 21; setp.eq.u32 %r34, %r27, 69; and.pred %r39, %r34, %r31; selp.u32 %value, 1, 0, %r39; This patch has been tested (on top of the patch mentioned above) on nvptx-none hosted on x86_64-pc-linux-gnu (including newlib) with a make and make -k check with no new failures. Ok for mainline? 2022-01-16 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * config/nvptx/nvptx.md (any_logic): Move code iterator earlier in machine description. (logic): Move code attribute earlier in machine description. (ilogic): New code attribute, like logic but "ior" for IOR. (and<mode>3, ior<mode>3, xor<mode>3): Delete. Replace with... (<ilogic><mode>3): New define_insn for HSDIM logic operations. (<ilogic>bi3): New define_insn for BI mode logic operations. (define_split): Lower logic operations from integer modes to BI mode predicate operations. gcc/testsuite/ChangeLog * gcc.target/nvptx/bool-2.c: New test case for and.pred. * gcc.target/nvptx/bool-3.c: New test case for or.pred. * gcc.target/nvptx/bool-4.c: New test case for xor.pred. Many thanks in advance. Roger --