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Wed, 17 Jun 2020 19:48:04 +0000 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 05HJm3ej53281062 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 17 Jun 2020 19:48:03 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8A7DA2805A; Wed, 17 Jun 2020 19:48:03 +0000 (GMT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6824F28058; Wed, 17 Jun 2020 19:48:03 +0000 (GMT) Received: from localhost (unknown [9.40.194.84]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 17 Jun 2020 19:48:03 +0000 (GMT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 26/28] rs6000: Add MASK_P9_VECTOR and MASK_P9_MISC builtins Date: Wed, 17 Jun 2020 14:46:49 -0500 Message-Id: <00e88ed99d34078bea857e49234546a6d7fdb389.1592419212.git.wschmidt@linux.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-06-17_10:2020-06-17, 2020-06-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=1 mlxscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 phishscore=0 adultscore=0 spamscore=0 bulkscore=0 priorityscore=1501 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2006170144 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Bill Schmidt via Gcc-patches From: Bill Schmidt Reply-To: Bill Schmidt Cc: dje.gcc@gmail.com, segher@kernel.crashing.org, willschm@linux.ibm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" 2020-06-17 Bill Schmidt * config/rs6000/rs6000-builtin-new.def: Add MASK_P9_VECTOR and MASK_P9_MISC builtins. --- gcc/config/rs6000/rs6000-builtin-new.def | 353 +++++++++++++++++++++++ 1 file changed, 353 insertions(+) diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def index e980e749d1d..d3e93f883fa 100644 --- a/gcc/config/rs6000/rs6000-builtin-new.def +++ b/gcc/config/rs6000/rs6000-builtin-new.def @@ -2393,3 +2393,356 @@ XSCVSPDPN vsx_xscvspdpn {} +; Power9 vector builtins. +[MASK_P9_VECTOR] + const vus __builtin_altivec_convert_4f32_8i16 (vf, vf); + CONVERT_4F32_8I16 convert_4f32_8i16 {} + + const unsigned int __builtin_altivec_first_match_index_v16qi (vsc, vsc); + VFIRSTMATCHINDEX_V16QI first_match_index_v16qi {} + + const unsigned int __builtin_altivec_first_match_index_v8hi (vss, vss); + VFIRSTMATCHINDEX_V8HI first_match_index_v8hi {} + + const unsigned int __builtin_altivec_first_match_index_v4si (vsi, vsi); + VFIRSTMATCHINDEX_V4SI first_match_index_v4si {} + + const unsigned int __builtin_altivec_first_match_or_eos_index_v16qi (vsc, vsc); + VFIRSTMATCHOREOSINDEX_V16QI first_match_or_eos_index_v16qi {} + + const unsigned int __builtin_altivec_first_match_or_eos_index_v8hi (vss, vss); + VFIRSTMATCHOREOSINDEX_V8HI first_match_or_eos_index_v8hi {} + + const unsigned int __builtin_altivec_first_match_or_eos_index_v4si (vsi, vsi); + VFIRSTMATCHOREOSINDEX_V4SI first_match_or_eos_index_v4si {} + + const unsigned int __builtin_altivec_first_mismatch_index_v16qi (vsc, vsc); + VFIRSTMISMATCHINDEX_V16QI first_mismatch_index_v16qi {} + + const unsigned int __builtin_altivec_first_mismatch_index_v8hi (vss, vss); + VFIRSTMISMATCHINDEX_V8HI first_mismatch_index_v8hi {} + + const unsigned int __builtin_altivec_first_mismatch_index_v4si (vsi, vsi); + VFIRSTMISMATCHINDEX_V4SI first_mismatch_index_v4si {} + + const unsigned int __builtin_altivec_first_mismatch_or_eos_index_v16qi (vsc, vsc); + VFIRSTMISMATCHOREOSINDEX_V16QI first_mismatch_or_eos_index_v16qi {} + + const unsigned int __builtin_altivec_first_mismatch_or_eos_index_v8hi (vss, vss); + VFIRSTMISMATCHOREOSINDEX_V8HI first_mismatch_or_eos_index_v8hi {} + + const unsigned int __builtin_altivec_first_mismatch_or_eos_index_v4si (vsi, vsi); + VFIRSTMISMATCHOREOSINDEX_V4SI first_mismatch_or_eos_index_v4si {} + + const vuc __builtin_altivec_vadub (vuc, vuc); + VADUB vaduv16qi3 {} + + const vus __builtin_altivec_vaduh (vus, vus); + VADUH vaduv8hi3 {} + + const vui __builtin_altivec_vaduw (vui, vui); + VADUW vaduv4si3 {} + + const vull __builtin_altivec_vbpermd (vull, vuc); + VBPERMD altivec_vbpermd {} + + const signed int __builtin_altivec_vclzlsbb_v16qi (vsc); + VCLZLSBB_V16QI vclzlsbb_v16qi {} + + const signed int __builtin_altivec_vclzlsbb_v4si (vsi); + VCLZLSBB_V4SI vclzlsbb_v4si {} + + const signed int __builtin_altivec_vclzlsbb_v8hi (vss); + VCLZLSBB_V8HI vclzlsbb_v8hi {} + + const vsc __builtin_altivec_vctzb (vsc); + VCTZB ctzv16qi2 {} + + const vsll __builtin_altivec_vctzd (vsll); + VCTZD ctzv2di2 {} + + const vss __builtin_altivec_vctzh (vss); + VCTZH ctzv8hi2 {} + + const vsi __builtin_altivec_vctzw (vsi); + VCTZW ctzv4si2 {} + + const signed int __builtin_altivec_vctzlsbb_v16qi (vsc); + VCTZLSBB_V16QI vctzlsbb_v16qi {} + + const signed int __builtin_altivec_vctzlsbb_v4si (vsi); + VCTZLSBB_V4SI vctzlsbb_v4si {} + + const signed int __builtin_altivec_vctzlsbb_v8hi (vss); + VCTZLSBB_V8HI vctzlsbb_v8hi {} + + const signed int __builtin_altivec_vcmpaeb_p (vsc, vsc); + VCMPAEB_P vector_ae_v16qi_p {pred} + + const signed int __builtin_altivec_vcmpaed_p (vsll, vsll); + VCMPAED_P vector_ae_v2di_p {pred} + + const signed int __builtin_altivec_vcmpaedp_p (vd, vd); + VCMPAEDP_P vector_ae_v2df_p {pred} + + const signed int __builtin_altivec_vcmpaefp_p (vf, vf); + VCMPAEFP_P vector_ae_v4sf_p {pred} + + const signed int __builtin_altivec_vcmpaeh_p (vss, vss); + VCMPAEH_P vector_ae_v8hi_p {pred} + + const signed int __builtin_altivec_vcmpaew_p (vsi, vsi); + VCMPAEW_P vector_ae_v4si_p {pred} + + const vbc __builtin_altivec_vcmpneb (vsc, vsc); + CMPNEB vcmpneb {} + + const signed int __builtin_altivec_vcmpneb_p (vsc, vsc); + VCMPNEB_P vector_ne_v16qi_p {pred} + + const signed int __builtin_altivec_vcmpned_p (vsll, vsll); + VCMPNED_P vector_ne_v2di_p {pred} + + const signed int __builtin_altivec_vcmpnedp_p (vd, vd); + VCMPNEDP_P vector_ne_v2df_p {pred} + + const signed int __builtin_altivec_vcmpnefp_p (vf, vf); + VCMPNEFP_P vector_ne_v4sf_p {pred} + + const vbs __builtin_altivec_vcmpneh (vss, vss); + CMPNEH vcmpneh {} + + const signed int __builtin_altivec_vcmpneh_p (vss, vss); + VCMPNEH_P vector_ne_v8hi_p {pred} + + const vbi __builtin_altivec_vcmpnew (vsi, vsi); + CMPNEW vcmpnew {} + + const signed int __builtin_altivec_vcmpnew_p (vsi, vsi); + VCMPNEW_P vector_ne_v4si_p {pred} + + const vbc __builtin_altivec_vcmpnezb (vsc, vsc); + CMPNEZB vcmpnezb {} + + const signed int __builtin_altivec_vcmpnezb_p (signed int, vsc, vsc); + VCMPNEZB_P vector_nez_v16qi_p {pred} + + const vbs __builtin_altivec_vcmpnezh (vss, vss); + CMPNEZH vcmpnezh {} + + const signed int __builtin_altivec_vcmpnezh_p (signed int, vss, vss); + VCMPNEZH_P vector_nez_v8hi_p {pred} + + const vbi __builtin_altivec_vcmpnezw (vsi, vsi); + CMPNEZW vcmpnezw {} + + const signed int __builtin_altivec_vcmpnezw_p (vsi, vsi); + VCMPNEZW_P vector_nez_v4si_p {pred} + + const unsigned char __builtin_altivec_vextublx (unsigned int, vuc); + VEXTUBLX vextublx {} + + const unsigned char __builtin_altivec_vextubrx (unsigned int, vuc); + VEXTUBRX vextubrx {} + + const unsigned short __builtin_altivec_vextuhlx (unsigned int, vus); + VEXTUHLX vextuhlx {} + + const unsigned short __builtin_altivec_vextuhrx (unsigned int, vus); + VEXTUHRX vextuhrx {} + + const unsigned int __builtin_altivec_vextuwlx (unsigned int, vui); + VEXTUWLX vextuwlx {} + + const unsigned int __builtin_altivec_vextuwrx (unsigned int, vui); + VEXTUWRX vextuwrx {} + + const vsll __builtin_altivec_vprtybd (vsll); + VPRTYBD parityv2di2 {} + + const vsq __builtin_altivec_vprtybq (vsq); + VPRTYBQ parityv1ti2 {} + + const vsi __builtin_altivec_vprtybw (vsi); + VPRTYBW parityv4si2 {} + + const vull __builtiin_altivec_vrldmi (vull, vull, vull); + VRLDMI altivec_vrldmi {} + + const vull __builtin_altivec_vrldnm (vull, vull); + VRLDNM altivec_vrldnm {} + + const vui __builtin_altivec_vrlwmi (vui, vui, vui); + VRLWMI altivec_vrlwmi {} + + const vui __builtin_altivec_vrlwnm (vui, vui); + VRLWNM altivec_vrlwnm {} + + const vuc __builtin_altivec_vslv (vuc, vuc); + VSLV vslv {} + + const vuc __builtin_altivec_vsrv (vuc, vuc); + VSRV vsrv {} + + const signed int __builtin_scalar_byte_in_range (unsigned char, unsigned int); + CMPRB cmprb {} + + const signed int __builtin_scalar_byte_in_either_range (unsigned char, unsigned int); + CMPRB2 cmprb2 {} + + const vull __builtin_vsx_extract4b (vuc, signed int); + EXTRACT4B extract4b {} + + const vull __builtin_vsx_extract_exp_dp (vd); + VEEDP xvxexpdp {} + + const vui __builtin_vsx_extract_exp_sp (vf); + VEESP xvxexpsp {} + + const vull __builtin_vsx_extract_sig_dp (vd); + VESDP xvxsigdp {} + + const vui __builtin_vsx_extract_sig_sp (vf); + VESSP xvxsigsp {} + + const vuc __builtin_vsx_insert4b (vsi, vuc, const int[0,12]); + INSERT4B insert4b {} + + const vd __builtin_vsx_insert_exp_dp (vop, vull); + VIEDP xviexpdp {} + + const vf __builtin_vsx_insert_exp_sp (vop, vull); + VIESP xviexpsp {} + + const signed int __builtin_vsx_scalar_cmp_exp_dp_eq (double, double); + VSCEDPEQ xscmpexpdp_eq {} + + const signed int __builtin_vsx_scalar_cmp_exp_dp_gt (double, double); + VSCEDPGT xscmpexpdp_gt {} + + const signed int __builtin_vsx_scalar_cmp_exp_dp_lt (double, double); + VSCEDPLT xscmpexpdp_lt {} + + const signed int __builtin_vsx_scalar_cmp_exp_dp_unordered (double, double); + VSCEDPUO xscmpexpdp_unordered {} + + const unsigned int __builtin_vsx_scalar_test_data_class_dp (double, signed int); + VSTDCDP xststdcdp {} + + const unsigned int __builtin_vsx_scalar_test_data_class_sp (float, signed int); + VSTDCSP xststdcsp {} + + const unsigned int __builtin_vsx_scalar_test_neg_dp (double); + VSTDCNDP xststdcnegdp {} + + const unsigned int __builtin_vsx_scalar_test_neg_sp (float); + VSTDCNSP xststdcnegsp {} + + const unsigned long long __builtin_vsx_test_data_class_dp (vd, signed int); + VTDCDP xvtstdcdp {} + + const unsigned int __builtin_vsx_test_data_class_sp (vf, signed int); + VTDCSP xvtstdcsp {} + + const vf __builtin_vsx_vextract_fp_from_shorth (vus); + VEXTRACT_FP_FROM_SHORTH vextract_fp_from_shorth {} + + const vf __builtin_vsx_vextract_fp_from_shortl (vus); + VEXTRACT_FP_FROM_SHORTL vextract_fp_from_shortl {} + + const vd __builtin_vsx_xxbrd_v2df (vd); + XXBRD_V2DF p9_xxbrd_v2df {} + + const vsll __builtin_vsx_xxbrd_v2di (vsll); + XXBRD_V2DI p9_xxbrd_v2di {} + + const vss __builtin_vsx_xxbrh_v8hi (vss); + XXBRH_V8HI p9_xxbrh_v8hi {} + + const vsc __builtin_vsx_xxbrq_v16qi (vsc); + XXBRQ_V16QI p9_xxbrq_v16qi {} + + const vsq __builtin_vsx_xxbrq_v1ti (vsq); + XXBRQ_V1TI p9_xxbrq_v1ti {} + + const vf __builtin_vsx_xxbrw_v4sf (vf); + XXBRW_V4SF p9_xxbrw_v4sf {} + + const vsi __builtin_vsx_xxbrw_v4si (vsi); + XXBRW_V4SI p9_xxbrw_v4si {} + + +[MASK_P9_MISC] + signed long long __builtin_darn (); + DARN darn {} + + signed int __builtin_darn_32 (); + DARN_32 darn_32 {} + + signed long long __builtin_darn_raw (); + DARN_RAW darn_raw {} + + const signed int __builtin_dtstsfi_eq_dd (unsigned int, _Decimal64); + TSTSFI_EQ_DD dfptstsfi_eq_dd {} + + const signed int __builtin_dtstsfi_eq_td (unsigned int, _Decimal128); + TSTSFI_EQ_TD dfptstsfi_eq_td {} + + const signed int __builtin_dtstsfi_gt_dd (unsigned int, _Decimal64); + TSTSFI_GT_DD dfptstsfi_gt_dd {} + + const signed int __builtin_dtstsfi_gt_td (unsigned int, _Decimal128); + TSTSFI_GT_TD dfptstsfi_gt_td {} + + const signed int __builtin_dtstsfi_lt_dd (unsigned int, _Decimal64); + TSTSFI_LT_DD dfptstsfi_lt_dd {} + + const signed int __builtin_dtstsfi_lt_td (unsigned int, _Decimal128); + TSTSFI_LT_TD dfptstsfi_lt_td {} + + const signed int __builtin_dtstsfi_ov_dd (unsigned int, _Decimal64); + TSTSFI_OV_DD dfptstsfi_unordered_dd {} + + const signed int __builtin_dtstsfi_ov_td (unsigned int, _Decimal128); + TSTSFI_OV_TD dfptstsfi_unordered_td {} + + +; These things need some review to see whether they really require +; MASK_POWERPC64. For xsxexpdp, this seems to be fine for 32-bit, +; because the result will always fit in 32 bits and the return +; value is SImode; but the pattern currently requires TARGET_64BIT. +; On the other hand, xsssigdp has a result that doesn't fit in +; 32 bits, and the return value is DImode, so it seems that +; TARGET_64BIT (actually TARGET_POWERPC64) is justified. TBD. #### +[(MASK_P9_VECTOR | MASK_POWERPC64)] +; The following two are inexplicably named __builtin_altivec_* while +; their load counterparts are __builtin_vsx_*. Need to deprecate +; these interfaces in favor of the other naming scheme (or vice versa). + void __builtin_altivec_xst_len_r (vop, void *, unsigned long long); + XST_LEN_R xst_len_r {} + + void __builtin_altivec_stxvl (vop, void *, unsigned long long); + STXVL stxvl {} + + const signed int __builtin_scalar_byte_in_set (unsigned char, unsigned long long); + CMPEQB cmpeqb {} + + pure vop __builtin_vsx_lxvl (void *, unsigned long long); + LXVL lxvl {} + + const unsigned int __builtin_vsx_scalar_extract_exp (double); + VSEEDP xsxexpdp {} + + const unsigned long long __builtin_vsx_scalar_extract_sig (double); + VSESDP xsxsigdp {} + + const double __builtin_vsx_scalar_insert_exp (unsigned long long, unsigned long long); + VSIEDP xsiexpdp {} + + const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long); + VSIEDPF xsiexpdpf {} + + pure vuc __builtin_vsx_xl_len_r (void *, unsigned long long); + XL_LEN_R xl_len_r {} + +