From patchwork Sun Nov 12 21:03:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 1862919 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nextmovesoftware.com header.i=@nextmovesoftware.com header.a=rsa-sha256 header.s=default header.b=d7QZEJFk; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4ST4mj45YWz1yRD for ; Mon, 13 Nov 2023 08:04:02 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2BF1D3858D20 for ; Sun, 12 Nov 2023 21:03:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id EB5ED3858D20 for ; Sun, 12 Nov 2023 21:03:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EB5ED3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EB5ED3858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=162.254.253.69 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699823026; cv=none; b=E36j88v/IrpulR/NBlpdVTqGZzJIZOVDlZ8v72jjV4nVLV4WSh4uuCxS5NKqKMgvxGCDWoMjCsZRv/BBUgaxgguC6qjthUJUXIjYUnGV90Wa5v4Z7gFL/26o43CqOqO6oJsLrD6n1SA4Imt/+IIzc9wCRWKcQ4SXF/3S/x5nJqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699823026; c=relaxed/simple; bh=ddFksJbvIdSonK4FhEA8YpwrBPLj3BiV2ZeNIbpjPEo=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=OYif+JDM+lgiNN8jj7cZFvnwMkYuJVmpwgVr9kuNq/u1t4APRDnz26dMwrQKOicfEq2KmEVth8GCF0immBD61f4LJ1Ivhz/cMpArhzPN5pelLOnLA6cpcEAd4OScgWjMb3gQHkM2abPLWlzov8oEaty20kNj8Xnx1z/M85YRf6U= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=c/u7VfzHq7zRdfBvHnnsE7JBJxl5I3pglzW0nuqVQH0=; b=d7QZEJFkVgzFEVwn/zscfKrzkr ZAl34E5maMNs8YOP6EsgQLc6/fIp02okH8akzfUigkZqH2TPZ3uCx5DhJH6n+lIriHhI+Dx4lo2wm NDSXLXbUYO9IziipPfJU/hibAu3vJ3X88OTUL9wQcnozD+1JZXYYLgFKUS+e4W4VpPbjuz5SfHu1Q ofNqxENy4N3hPYYHeZL/uCbJ1cTG6loTezK2/+LCh/dTxPlN/qPPvfrso743f+wjCq2ZzfDmyQe0W XK4z2PkvT8PlpeIru2m90HAtCPjCVPLLY1Q8oKR9+6Xbk1jYe/wX4bDS6lFiGzRRwvMdICEq8mLXY 5nt8bPYA==; Received: from [109.144.214.163] (port=53249 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1r2HcO-0001iP-0X; Sun, 12 Nov 2023 16:03:44 -0500 From: "Roger Sayle" To: Cc: "'Uros Bizjak'" Subject: [x86 PATCH] Improve reg pressure of double-word right-shift then truncate. Date: Sun, 12 Nov 2023 21:03:42 -0000 Message-ID: <00d701da15ab$b8971170$29c53450$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdoVqySDuNH34rlJR42QnRpLwLImeQ== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LOTS_OF_MONEY, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch improves register pressure during reload, inspired by PR 97756. Normally, a double-word right-shift by a constant produces a double-word result, the highpart of which is dead when followed by a truncation. The dead code calculating the high part gets cleaned up post-reload, so the issue isn't normally visible, except for the increased register pressure during reload, sometimes leading to odd register assignments. Providing a post-reload splitter, which clobbers a single wordmode result register instead of a doubleword result register, helps (a bit). An example demonstrating this effect is: #define MASK60 ((1ul << 60) - 1) unsigned long foo (__uint128_t n) { unsigned long a = n & MASK60; unsigned long b = (n >> 60); b = b & MASK60; unsigned long c = (n >> 120); return a+b+c; } which currently with -O2 generates (13 instructions): foo: movabsq $1152921504606846975, %rcx xchgq %rdi, %rsi movq %rsi, %rax shrdq $60, %rdi, %rax movq %rax, %rdx movq %rsi, %rax movq %rdi, %rsi andq %rcx, %rax shrq $56, %rsi andq %rcx, %rdx addq %rsi, %rax addq %rdx, %rax ret with this patch, we generate one less mov (12 instructions): foo: movabsq $1152921504606846975, %rcx xchgq %rdi, %rsi movq %rdi, %rdx movq %rsi, %rax movq %rdi, %rsi shrdq $60, %rdi, %rdx andq %rcx, %rax shrq $56, %rsi addq %rsi, %rax andq %rcx, %rdx addq %rdx, %rax ret The significant difference is easier to see via diff: < shrdq $60, %rdi, %rax < movq %rax, %rdx --- > shrdq $60, %rdi, %rdx Admittedly a single "mov" isn't much of a saving on modern architectures, but as demonstrated by the PR, people still track the number of them. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32} with no new failures. Ok for mainline? 2023-11-12 Roger Sayle gcc/ChangeLog * config/i386/i386.md (3_doubleword_lowpart): New define_insn_and_split to optimize register usage of doubleword right shifts followed by truncation. Thanks in advance, Roger -- diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 663db73..8a6928f 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -14833,6 +14833,31 @@ [(const_int 0)] "ix86_split_ (operands, operands[3], mode); DONE;") +;; Split truncations of TImode right shifts into x86_64_shrd_1. +;; Split truncations of DImode right shifts into x86_shrd_1. +(define_insn_and_split "3_doubleword_lowpart" + [(set (match_operand:DWIH 0 "register_operand" "=&r") + (subreg:DWIH + (any_shiftrt: (match_operand: 1 "register_operand" "r") + (match_operand:QI 2 "const_int_operand")) 0)) + (clobber (reg:CC FLAGS_REG))] + "UINTVAL (operands[2]) < * BITS_PER_UNIT" + "#" + "&& reload_completed" + [(parallel + [(set (match_dup 0) + (ior:DWIH (lshiftrt:DWIH (match_dup 0) (match_dup 2)) + (subreg:DWIH + (ashift: (zero_extend: (match_dup 3)) + (match_dup 4)) 0))) + (clobber (reg:CC FLAGS_REG))])] +{ + split_double_mode (mode, &operands[1], 1, &operands[1], &operands[3]); + operands[4] = GEN_INT (( * BITS_PER_UNIT) - INTVAL (operands[2])); + if (!rtx_equal_p (operands[0], operands[3])) + emit_move_insn (operands[0], operands[3]); +}) + (define_insn "x86_64_shrd" [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m") (ior:DI (lshiftrt:DI (match_dup 0)