From patchwork Sat Jul 22 15:37:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 1811299 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nextmovesoftware.com header.i=@nextmovesoftware.com header.a=rsa-sha256 header.s=default header.b=TSi98rii; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R7Vtd6jN4z1yZ7 for ; Sun, 23 Jul 2023 01:37:59 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D7E9F3860764 for ; Sat, 22 Jul 2023 15:37:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id A42C93858D1E for ; Sat, 22 Jul 2023 15:37:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A42C93858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=2Fx4a1CBYUPbxlJboW10ebxgx7UEmhFx8Fsjeoyf4pc=; b=TSi98riizVOIolxk1HAiClXwmn S77GmMRF/Q27EJdJImeawShUYaePH98dyMzqJ4L3Pc0BH5+gjM4zYXZUbcCOIkJkztrVOTTvzx9MH IU6EKhX9rsXyM1kVzZJ+K+tyYGNUwVIgkXtSnYcSaXtMVyUBlkWrwn9FLJ4zlyKBwOkQIMr00mIRN yDR7TZZmUY3kIvh2otW0sd1as7Szr4wV35GAAKmXK4DIHq7bK0nl/yiUPbA7YJfCSWsJ3TVIUbH2P el8gal9ftIgg6YGG0cYKV60vt82CXCp3uYupxaqfIx8vJFzCVela5XatO2+lt9ws1LMUwPXTSDug9 aEWzC0KA==; Received: from [185.62.158.67] (port=60445 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1qNEfs-0004Pf-2m; Sat, 22 Jul 2023 11:37:41 -0400 From: "Roger Sayle" To: Cc: "'Uros Bizjak'" Subject: [x86 PATCH] Use QImode for offsets in zero_extract/sign_extract in i386.md Date: Sat, 22 Jul 2023 16:37:39 +0100 Message-ID: <00c701d9bcb2$733bcdc0$59b36940$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: Adm8scYiwRswnYpSRnOPbpywNdjIMA== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, MEDICAL_SUBJECT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" As suggested by Uros, this patch changes the ZERO_EXTRACTs and SIGN_EXTRACTs in i386.md to consistently use QImode for bit offsets (i.e. third and fourth operands), matching the use of QImode for bit counts in shifts and rotates. There's no change in functionality, and the new patterns simply ensure that we continue to generate the same code (match revised patterns) as before. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32} with no new failures. Ok for mainline? 2023-07-22 Roger Sayle gcc/ChangeLog * config/i386/i386.md (extv): Use QImode for offsets. (extzv): Likewise. (insv): Likewise. (*testqi_ext_3): Likewise. (*btr_2): Likewise. (define_split): Likewise. (*btsq_imm): Likewise. (*btrq_imm): Likewise. (*btcq_imm): Likewise. (define_peephole2 x3): Likewise. (*bt): Likewise (*bt_mask): New define_insn_and_split. (*jcc_bt): Use QImode for offsets. (*jcc_bt_1): Delete obsolete pattern. (*jcc_bt_mask): Use QImode offsets. (*jcc_bt_mask_1): Likewise. (define_split): Likewise. (*bt_setcqi): Likewise. (*bt_setncqi): Likewise. (*bt_setnc): Likewise. (*bt_setncqi_2): Likewise. (*bt_setc_mask): New define_insn_and_split. (bmi2_bzhi_3): Use QImode offsets. (*bmi2_bzhi_3): Likewise. (*bmi2_bzhi_3_1): Likewise. (*bmi2_bzhi_3_1_ccz): Likewise. (@tbm_bextri_): Likewise. Thanks, Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 47ea050..de8c3a5 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3312,8 +3312,8 @@ (define_expand "extv" [(set (match_operand:SWI24 0 "register_operand") (sign_extract:SWI24 (match_operand:SWI24 1 "register_operand") - (match_operand:SI 2 "const_int_operand") - (match_operand:SI 3 "const_int_operand")))] + (match_operand:QI 2 "const_int_operand") + (match_operand:QI 3 "const_int_operand")))] "" { /* Handle extractions from %ah et al. */ @@ -3340,8 +3340,8 @@ (define_expand "extzv" [(set (match_operand:SWI248 0 "register_operand") (zero_extract:SWI248 (match_operand:SWI248 1 "register_operand") - (match_operand:SI 2 "const_int_operand") - (match_operand:SI 3 "const_int_operand")))] + (match_operand:QI 2 "const_int_operand") + (match_operand:QI 3 "const_int_operand")))] "" { if (ix86_expand_pextr (operands)) @@ -3428,8 +3428,8 @@ (define_expand "insv" [(set (zero_extract:SWI248 (match_operand:SWI248 0 "register_operand") - (match_operand:SI 1 "const_int_operand") - (match_operand:SI 2 "const_int_operand")) + (match_operand:QI 1 "const_int_operand") + (match_operand:QI 2 "const_int_operand")) (match_operand:SWI248 3 "register_operand"))] "" { @@ -10788,8 +10788,8 @@ (match_operator 1 "compare_operator" [(zero_extract:SWI248 (match_operand 2 "int_nonimmediate_operand" "rm") - (match_operand 3 "const_int_operand") - (match_operand 4 "const_int_operand")) + (match_operand:QI 3 "const_int_operand") + (match_operand:QI 4 "const_int_operand")) (const_int 0)]))] "/* Ensure that resulting mask is zero or sign extended operand. */ INTVAL (operands[4]) >= 0 @@ -15904,7 +15904,7 @@ [(set (zero_extract:HI (match_operand:SWI12 0 "nonimmediate_operand") (const_int 1) - (zero_extend:SI (match_operand:QI 1 "register_operand"))) + (match_operand:QI 1 "register_operand")) (const_int 0)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT && ix86_pre_reload_split ()" @@ -15928,7 +15928,7 @@ [(set (zero_extract:HI (match_operand:SWI12 0 "register_operand") (const_int 1) - (zero_extend:SI (match_operand:QI 1 "register_operand"))) + (match_operand:QI 1 "register_operand")) (const_int 0)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT && ix86_pre_reload_split ()" @@ -15955,7 +15955,7 @@ (define_insn "*btsq_imm" [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm") (const_int 1) - (match_operand 1 "const_0_to_63_operand")) + (match_operand:QI 1 "const_0_to_63_operand")) (const_int 1)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -15968,7 +15968,7 @@ (define_insn "*btrq_imm" [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm") (const_int 1) - (match_operand 1 "const_0_to_63_operand")) + (match_operand:QI 1 "const_0_to_63_operand")) (const_int 0)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -15981,7 +15981,7 @@ (define_insn "*btcq_imm" [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm") (const_int 1) - (match_operand 1 "const_0_to_63_operand")) + (match_operand:QI 1 "const_0_to_63_operand")) (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1)))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -15998,7 +15998,7 @@ (parallel [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand") (const_int 1) - (match_operand 1 "const_0_to_63_operand")) + (match_operand:QI 1 "const_0_to_63_operand")) (const_int 1)) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" @@ -16022,7 +16022,7 @@ (parallel [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand") (const_int 1) - (match_operand 1 "const_0_to_63_operand")) + (match_operand:QI 1 "const_0_to_63_operand")) (const_int 0)) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" @@ -16046,7 +16046,7 @@ (parallel [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand") (const_int 1) - (match_operand 1 "const_0_to_63_operand")) + (match_operand:QI 1 "const_0_to_63_operand")) (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1)))) (clobber (reg:CC FLAGS_REG))])] @@ -16074,14 +16074,14 @@ (zero_extract:SWI48 (match_operand:SWI48 0 "nonimmediate_operand" "r,m") (const_int 1) - (match_operand:SI 1 "nonmemory_operand" "r,")) + (match_operand:QI 1 "nonmemory_operand" "q,")) (const_int 0)))] "" { switch (get_attr_mode (insn)) { case MODE_SI: - return "bt{l}\t{%1, %k0|%k0, %1}"; + return "bt{l}\t{%k1, %k0|%k0, %k1}"; case MODE_DI: return "bt{q}\t{%q1, %0|%0, %q1}"; @@ -16099,13 +16099,36 @@ (const_string "SI") (const_string "")))]) +(define_insn_and_split "*bt_mask" + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (zero_extract:SWI48 + (match_operand:SWI48 0 "nonimmediate_operand" "r,m") + (const_int 1) + (subreg:QI + (and:SWI248 + (match_operand:SWI248 1 "register_operand") + (match_operand 2 "const_int_operand")) 0)) + (const_int 0)))] + "TARGET_USE_BT + && (INTVAL (operands[2]) & (GET_MODE_BITSIZE (mode)-1)) + == GET_MODE_BITSIZE (mode)-1 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (zero_extract:SWI48 (match_dup 0) (const_int 1) (match_dup 1)) + (const_int 0)))] + "operands[1] = gen_lowpart (QImode, operands[1]);") + (define_insn_and_split "*jcc_bt" [(set (pc) (if_then_else (match_operator 0 "bt_comparison_operator" [(zero_extract:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") (const_int 1) - (match_operand:SI 2 "nonmemory_operand")) + (match_operand:QI 2 "nonmemory_operand")) (const_int 0)]) (label_ref (match_operand 3)) (pc))) @@ -16135,39 +16158,6 @@ PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); }) -(define_insn_and_split "*jcc_bt_1" - [(set (pc) - (if_then_else (match_operator 0 "bt_comparison_operator" - [(zero_extract:SWI48 - (match_operand:SWI48 1 "register_operand") - (const_int 1) - (zero_extend:SI - (match_operand:QI 2 "register_operand"))) - (const_int 0)]) - (label_ref (match_operand 3)) - (pc))) - (clobber (reg:CC FLAGS_REG))] - "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) - && ix86_pre_reload_split ()" - "#" - "&& 1" - [(set (reg:CCC FLAGS_REG) - (compare:CCC - (zero_extract:SWI48 - (match_dup 1) - (const_int 1) - (match_dup 2)) - (const_int 0))) - (set (pc) - (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)]) - (label_ref (match_dup 3)) - (pc)))] -{ - operands[2] = lowpart_subreg (SImode, operands[2], QImode); - operands[0] = shallow_copy_rtx (operands[0]); - PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); -}) - ;; Avoid useless masking of bit offset operand. (define_insn_and_split "*jcc_bt_mask" [(set (pc) @@ -16175,8 +16165,8 @@ [(zero_extract:SWI48 (match_operand:SWI48 1 "register_operand") (const_int 1) - (and:SI - (match_operand:SI 2 "register_operand") + (and:QI + (match_operand:QI 2 "register_operand") (match_operand 3 "const_int_operand")))]) (label_ref (match_operand 4)) (pc))) @@ -16203,23 +16193,23 @@ PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); }) -(define_insn_and_split "*jcc_bt_mask_1" +;; Avoid useless masking of bit offset operand. +(define_insn_and_split "*jcc_bt_mask_1" [(set (pc) - (if_then_else (match_operator 0 "bt_comparison_operator" + (if_then_else (match_operator 0 "bt_comparison_operator" [(zero_extract:SWI48 (match_operand:SWI48 1 "register_operand") (const_int 1) - (zero_extend:SI - (subreg:QI - (and - (match_operand 2 "int248_register_operand") - (match_operand 3 "const_int_operand")) 0)))]) + (subreg:QI + (and:SWI248 + (match_operand:SWI248 2 "register_operand") + (match_operand 3 "const_int_operand")) 0))]) (label_ref (match_operand 4)) (pc))) (clobber (reg:CC FLAGS_REG))] "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) - && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) - == GET_MODE_BITSIZE (mode)-1 + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) + == GET_MODE_BITSIZE (mode)-1 && ix86_pre_reload_split ()" "#" "&& 1" @@ -16235,10 +16225,9 @@ (label_ref (match_dup 4)) (pc)))] { - operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); - operands[2] = gen_lowpart (SImode, operands[2]); operands[0] = shallow_copy_rtx (operands[0]); PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0]))); + operands[2] = gen_lowpart (QImode, operands[2]); }) ;; Help combine recognize bt followed by cmov @@ -16249,7 +16238,7 @@ [(zero_extract:SWI48 (match_operand:SWI48 1 "register_operand") (const_int 1) - (zero_extend:SI (match_operand:QI 2 "register_operand"))) + (match_operand:QI 2 "register_operand")) (const_int 0)]) (match_operand:SWI248 3 "nonimmediate_operand") (match_operand:SWI248 4 "nonimmediate_operand")))] @@ -16267,7 +16256,6 @@ { if (GET_CODE (operands[5]) == EQ) std::swap (operands[3], operands[4]); - operands[2] = lowpart_subreg (SImode, operands[2], QImode); }) ;; Help combine recognize bt followed by setc @@ -16276,7 +16264,7 @@ (zero_extract:SWI48 (match_operand:SWI48 1 "register_operand") (const_int 1) - (zero_extend:SI (match_operand:QI 2 "register_operand")))) + (match_operand:QI 2 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT && ix86_pre_reload_split ()" "#" @@ -16286,8 +16274,7 @@ (zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) - (eq:QI (reg:CCC FLAGS_REG) (const_int 0)))] - "operands[2] = lowpart_subreg (SImode, operands[2], QImode);") + (eq:QI (reg:CCC FLAGS_REG) (const_int 0)))]) ;; Help combine recognize bt followed by setnc (define_insn_and_split "*bt_setncqi" @@ -16307,8 +16294,7 @@ (zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) - (ne:QI (reg:CCC FLAGS_REG) (const_int 0)))] - "operands[2] = lowpart_subreg (SImode, operands[2], QImode);") + (ne:QI (reg:CCC FLAGS_REG) (const_int 0)))]) (define_insn_and_split "*bt_setnc" [(set (match_operand:SWI48 0 "register_operand") @@ -16328,10 +16314,7 @@ (set (match_dup 3) (ne:QI (reg:CCC FLAGS_REG) (const_int 0))) (set (match_dup 0) (zero_extend:SWI48 (match_dup 3)))] -{ - operands[2] = lowpart_subreg (SImode, operands[2], QImode); - operands[3] = gen_reg_rtx (QImode); -}) + "operands[3] = gen_reg_rtx (QImode);") ;; Help combine recognize bt followed by setnc (PR target/110588) (define_insn_and_split "*bt_setncqi_2" @@ -16340,7 +16323,7 @@ (zero_extract:SWI48 (match_operand:SWI48 1 "register_operand") (const_int 1) - (zero_extend:SI (match_operand:QI 2 "register_operand"))) + (match_operand:QI 2 "register_operand")) (const_int 0))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT && ix86_pre_reload_split ()" @@ -16351,8 +16334,36 @@ (zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) - (ne:QI (reg:CCC FLAGS_REG) (const_int 0)))] - "operands[2] = lowpart_subreg (SImode, operands[2], QImode);") + (ne:QI (reg:CCC FLAGS_REG) (const_int 0)))]) + +;; Help combine recognize bt followed by setc +(define_insn_and_split "*bt_setc_mask" + [(set (match_operand:SWI48 0 "register_operand") + (zero_extract:SWI48 + (match_operand:SWI48 1 "register_operand") + (const_int 1) + (subreg:QI + (and:SWI48 + (match_operand:SWI48 2 "register_operand") + (match_operand 3 "const_int_operand")) 0))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_USE_BT + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) + == GET_MODE_BITSIZE (mode)-1 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2)) + (const_int 0))) + (set (match_dup 3) + (ne:QI (reg:CCC FLAGS_REG) (const_int 0))) + (set (match_dup 0) (zero_extend:SWI48 (match_dup 3)))] +{ + operands[2] = gen_lowpart (QImode, operands[2]); + operands[3] = gen_reg_rtx (QImode); +}) ;; Store-flag instructions. @@ -18647,46 +18658,29 @@ [(parallel [(set (match_operand:SWI48 0 "register_operand") (if_then_else:SWI48 - (ne:QI (and:SWI48 (match_operand:SWI48 2 "register_operand") - (const_int 255)) + (ne:QI (match_operand:QI 2 "register_operand") (const_int 0)) (zero_extract:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") - (umin:SWI48 (and:SWI48 (match_dup 2) (const_int 255)) - (match_dup 3)) + (umin:QI (match_dup 2) (match_dup 3)) (const_int 0)) (const_int 0))) (clobber (reg:CC FLAGS_REG))])] "TARGET_BMI2" - "operands[3] = GEN_INT ( * BITS_PER_UNIT);") +{ + operands[2] = gen_lowpart (QImode, operands[2]); + operands[3] = GEN_INT ( * BITS_PER_UNIT); +}) (define_insn "*bmi2_bzhi_3" [(set (match_operand:SWI48 0 "register_operand" "=r") (if_then_else:SWI48 - (ne:QI (and:SWI48 (match_operand:SWI48 2 "register_operand" "r") - (const_int 255)) + (ne:QI (match_operand:QI 2 "register_operand" "q") (const_int 0)) (zero_extract:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") - (umin:SWI48 (and:SWI48 (match_dup 2) (const_int 255)) - (match_operand:SWI48 3 "const_int_operand")) - (const_int 0)) - (const_int 0))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_BMI2 && INTVAL (operands[3]) == * BITS_PER_UNIT" - "bzhi\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "bitmanip") - (set_attr "prefix" "vex") - (set_attr "mode" "")]) - -(define_insn "*bmi2_bzhi_3_1" - [(set (match_operand:SWI48 0 "register_operand" "=r") - (if_then_else:SWI48 - (ne:QI (match_operand:QI 2 "register_operand" "r") (const_int 0)) - (zero_extract:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand" "rm") - (umin:SWI48 (zero_extend:SWI48 (match_dup 2)) - (match_operand:SWI48 3 "const_int_operand")) + (umin:QI (match_dup 2) + (match_operand:QI 3 "const_int_operand")) (const_int 0)) (const_int 0))) (clobber (reg:CC FLAGS_REG))] @@ -18703,8 +18697,8 @@ (ne:QI (match_operand:QI 2 "register_operand" "r") (const_int 0)) (zero_extract:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") - (umin:SWI48 (zero_extend:SWI48 (match_dup 2)) - (match_operand:SWI48 3 "const_int_operand")) + (umin:QI (match_dup 2) + (match_operand:QI 3 "const_int_operand")) (const_int 0)) (const_int 0)) (const_int 0))) @@ -18803,8 +18797,8 @@ [(set (match_operand:SWI48 0 "register_operand" "=r") (zero_extract:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") - (match_operand 2 "const_0_to_255_operand") - (match_operand 3 "const_0_to_255_operand"))) + (match_operand:QI 2 "const_0_to_255_operand") + (match_operand:QI 3 "const_0_to_255_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_TBM" {