diff mbox series

Improved SUBREG simplifications in simplify-rtx.cc's simplify_subreg.

Message ID 008401d9a1ce$d46257d0$7d270770$@nextmovesoftware.com
State New
Headers show
Series Improved SUBREG simplifications in simplify-rtx.cc's simplify_subreg. | expand

Commit Message

Roger Sayle June 18, 2023, 10:22 a.m. UTC 
An x86 backend improvement that I'm working results in combine attempting
to recognize:

(set (reg:DI 87 [ xD.2846 ])
     (ior:DI (subreg:DI (ashift:TI (zero_extend:TI (reg:DI 92))
                                   (const_int 64 [0x40])) 0)
             (reg:DI 91)))

where the lowpart SUBREG has difficulty seeing through the (hi<<64)
that the lowpart must be zero.  Rather than workaround this in the
backend, the better fix is to teach simplify-rtx that
lowpart((hi<<64)|lo) -> lo and highpart((hi<<64)|lo) -> hi, so that
all backends benefit.  Reducing the number of places where the
middle-end generates a SUBREG of something other than REG is a
good thing.

This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check, both with and without --target_board=unix{-m32}
with no new failures, except for pr78904-1b.c, for which a backend
solution has just been proposed.  Ok for mainline?


2023-06-18  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
        * simplify-rtx.cc (simplify_subreg):  Optimize lowpart SUBREGs
        of ASHIFT to const0_rtx with sufficiently large shift count.
        Optimize highpart SUBREGs of ASHIFT as the shift operand when
        the shift count is the correct offset.  Optimize SUBREGs of
        multi-word logic operations if the SUBREGs of both operands
        can be simplified.


Thanks in advance,
Roger
--

Comments

Jeff Law June 19, 2023, 1:54 p.m. UTC | #1 
On 6/18/23 04:22, Roger Sayle wrote:
> 
> An x86 backend improvement that I'm working results in combine attempting
> to recognize:
> 
> (set (reg:DI 87 [ xD.2846 ])
>       (ior:DI (subreg:DI (ashift:TI (zero_extend:TI (reg:DI 92))
>                                     (const_int 64 [0x40])) 0)
>               (reg:DI 91)))
> 
> where the lowpart SUBREG has difficulty seeing through the (hi<<64)
> that the lowpart must be zero.  Rather than workaround this in the
> backend, the better fix is to teach simplify-rtx that
> lowpart((hi<<64)|lo) -> lo and highpart((hi<<64)|lo) -> hi, so that
> all backends benefit.  Reducing the number of places where the
> middle-end generates a SUBREG of something other than REG is a
> good thing.
> 
> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
> and make -k check, both with and without --target_board=unix{-m32}
> with no new failures, except for pr78904-1b.c, for which a backend
> solution has just been proposed.  Ok for mainline?
> 
> 
> 2023-06-18  Roger Sayle  <roger@nextmovesoftware.com>
> 
> gcc/ChangeLog
>          * simplify-rtx.cc (simplify_subreg):  Optimize lowpart SUBREGs
>          of ASHIFT to const0_rtx with sufficiently large shift count.
>          Optimize highpart SUBREGs of ASHIFT as the shift operand when
>          the shift count is the correct offset.  Optimize SUBREGs of
>          multi-word logic operations if the SUBREGs of both operands
>          can be simplified.
OK
Jeff
diff mbox series

Patch

diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index 21b7eb4..6715247 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -7746,6 +7746,38 @@  simplify_context::simplify_subreg (machine_mode outermode, rtx op,
 	return CONST0_RTX (outermode);
     }
 
+  /* Optimize SUBREGS of scalar integral ASHIFT by a valid constant.  */
+  if (GET_CODE (op) == ASHIFT
+      && SCALAR_INT_MODE_P (innermode)
+      && CONST_INT_P (XEXP (op, 1))
+      && INTVAL (XEXP (op, 1)) > 0
+      && known_gt (GET_MODE_BITSIZE (innermode), INTVAL (XEXP (op, 1))))
+    {
+      HOST_WIDE_INT val = INTVAL (XEXP (op, 1));
+      /* A lowpart SUBREG of a ASHIFT by a constant may fold to zero.  */
+      if (known_eq (subreg_lowpart_offset (outermode, innermode), byte)
+	  && known_le (GET_MODE_BITSIZE (outermode), val))
+        return CONST0_RTX (outermode);
+      /* Optimize the highpart SUBREG of a suitable ASHIFT (ZERO_EXTEND).  */
+      if (GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
+	  && GET_MODE (XEXP (XEXP (op, 0), 0)) == outermode
+	  && known_eq (GET_MODE_BITSIZE (outermode), val)
+	  && known_eq (GET_MODE_BITSIZE (innermode), 2 * val)
+	  && known_eq (subreg_highpart_offset (outermode, innermode), byte))
+	return XEXP (XEXP (op, 0), 0);
+    }
+
+  /* Attempt to simplify WORD_MODE SUBREGs of bitwise expressions.  */
+  if (outermode == word_mode
+      && (GET_CODE (op) == IOR || GET_CODE (op) == XOR || GET_CODE (op) == AND)
+      && SCALAR_INT_MODE_P (innermode))
+    {
+      rtx op0 = simplify_subreg (outermode, XEXP (op, 0), innermode, byte);
+      rtx op1 = simplify_subreg (outermode, XEXP (op, 1), innermode, byte);
+      if (op0 && op1)
+	return simplify_gen_binary (GET_CODE (op), outermode, op0, op1);
+    }
+
   scalar_int_mode int_outermode, int_innermode;
   if (is_a <scalar_int_mode> (outermode, &int_outermode)
       && is_a <scalar_int_mode> (innermode, &int_innermode)