From patchwork Thu Dec 17 09:39:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 558156 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BB89C1401DE for ; Thu, 17 Dec 2015 20:39:43 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=VcinIccN; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=i1tNkqiYPEaRCUJV 9ZQ3dH/HJTu/CO3HIrobKsFomjp8yl0Iktb0Oem0ztJFNsxnxTdaEHMsYhiP7NYB sLfzBiuFU0IS4M5Vmmz7/zbUSd8zMdfIPrf56gDgtPRbjR3FLpLwn/lt1JhVbVjO BGde5CO+Xe2dVkLIf9PPr0vwlXs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=KVbMRsjL50wsYI0MogmeUE 6BsiM=; b=VcinIccNiKUSaClGE7izFCoCRMDG1heAGGR3nkBjyW6U9vR553ZTKU PT3pQrNcOT8DAfshYCDC8OqHi0exnlw82+Hmoo1i3stA94OSaiVHRzDpcmm43PkD H4VsMkozrf0dD91K1cz3KyRApONXufwpqppaGUzU7ZxYiQMsXGmcg= Received: (qmail 97570 invoked by alias); 17 Dec 2015 09:39:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 97524 invoked by uid 89); 17 Dec 2015 09:39:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.1 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, T_RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=chip, UD:libgcov.a, libma, libnosysa X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 17 Dec 2015 09:39:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9CD7A55D; Thu, 17 Dec 2015 01:39:09 -0800 (PST) Received: from SHAWIN202 (unknown [10.164.12.31]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 611333F21A; Thu, 17 Dec 2015 01:39:31 -0800 (PST) From: "Thomas Preud'homme" To: , "Richard Earnshaw" , "Ramana Radhakrishnan" , "Kyrylo Tkachov" Subject: [PATCH, ARM 7/6] Enable atomics for ARMv8-M Mainline Date: Thu, 17 Dec 2015 17:39:29 +0800 Message-ID: <006a01d138ae$d5014430$7f03cc90$@foss.arm.com> MIME-Version: 1.0 Hi, This patch is part of a patch series to add support for ARMv8-M[1] to GCC. This specific patch enable atomics for ARMv8-M Mainline. No change is needed to existing patterns since Thumb-2 backend can already handle them fine. [1] For a quick overview of ARMv8-M please refer to the initial cover letter. ChangeLog entries are as follow: *** gcc/ChangeLog *** 2015-12-17 Thomas Preud'homme * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline. Testing: * Toolchain was built successfully with and without the ARMv8-M support patches with the following multilib list: armv6-m,armv7-m,armv7e-m,cortex-m7. The code generation for crtbegin.o, crtend.o, crti.o, crtn.o, libgcc.a, libgcov.a, libc.a, libg.a, libgloss-linux.a, libm.a, libnosys.a, librdimon.a, librdpmon.a, libstdc++.a and libsupc++.a is unchanged for all these targets. * GCC also showed no testsuite regression when targeting ARMv8-M Baseline compared to ARMv6-M on ARM Fast Models and when targeting ARMv6-M and ARMv7-M (compared to without the patch) * GCC was bootstrapped successfully targeting Thumb-1 and targeting Thumb-2 Is this ok for stage3? Best regards, Thomas diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 1f79c37b5c36a410a2d500ba92c62a5ba4ca1178..fa2a6fb03ffd2ca53bfb7e7c8f03022b626880e0 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -258,7 +258,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void); || arm_arch7) && arm_arch_notm) /* Nonzero if this chip supports load-acquire and store-release. */ -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm) +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT) /* Nonzero if this chip provides the movw and movt instructions. */ #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8)