From patchwork Thu Jul 11 18:45:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 1959487 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nextmovesoftware.com header.i=@nextmovesoftware.com header.a=rsa-sha256 header.s=default header.b=bLvzxmNX; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WKkFT6LQVz1xqc for ; Fri, 12 Jul 2024 04:45:49 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EFA0038754BB for ; Thu, 11 Jul 2024 18:45:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [69.48.154.134]) by sourceware.org (Postfix) with ESMTPS id 6D168387545A for ; Thu, 11 Jul 2024 18:45:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6D168387545A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6D168387545A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=69.48.154.134 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1720723528; cv=none; b=BqOCDU6w8AU1QoLNsPTliT1io7kkki34xZcK0uPiscemcsTDzMNmqeZZCLwpXViMFD4U67PYKIntJ3rxHYgB1FYEiKWHNoZq/vQKVNjAqLc1lIxkuXOVoz/uO/HAUsBLbNR6ijGviFYjoNdvxxBZaY27HQQClJ1E6tq/YuZH9CM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1720723528; c=relaxed/simple; bh=mo4XvIB2LQG7ALzgwdIXUzFgNo+4uLlGJRFJJnKvMsw=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=mx1Rl5NSqujOzKY4GVrBMygjSFV4QXm+M8vyc1dB6b6tsxeTkxqID04miWWhnOA9DhT3+zgJoJtTjHm/0pMMTy3qhIrwBM86zgNmr2fzjCF5byGzCRXZu3R1LhRbjmttSOsOlcgmAQ0MPyoIn2JsUtp4CZ6COn954JYZkV09o5I= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=VRlKg9g1JX483Ae9eea8Xwn89I9evFv8gN8F/SvgPJA=; b=bLvzxmNXsCVSAg6IyFamL83cIu 8jawJ4J8T62e3kgZ0WvM2m7zykiIQYX0gt1v1zRnIbsB1Me8/OM5i4f8P0IsxL3mI95xyhByGOaoZ voggRX2ECAcCUkZkZvU7xRP+pdfpY7P+ta+99WHokr9MjTEO06/jXsMbkQkUgzMbzKMgqGCXS7gJT 2FUQ6OFVRPASlHpFBrGcNy4dFPI0tz92ZwqmtGxH5Ximy+buTMiKQtxNPuBmfxTZY5u1cBAc6krGD cLaY0bKRwE+sTRESC6Va9ZmhE/G1eNViooG5Ow/Ct2edQBGFP5OOAcAiMUlnWuj8gQ48skBKiEokf GI6ru1UA==; Received: from [168.86.198.82] (port=55815 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1sRynB-00000000hzM-3pBf; Thu, 11 Jul 2024 14:45:22 -0400 From: "Roger Sayle" To: Cc: "'Claudiu Zissulescu'" Subject: [ARC PATCH] Improve performance of SImode right shifts. Date: Thu, 11 Jul 2024 19:45:20 +0100 Message-ID: <005601dad3c2$7bdc4400$7394cc00$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdrTwKL0yyTdhC6kSFuoU1Q6q30j9g== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch improves the speed of ARC's ashrsi3 and lshrsi3, on CPUs without a barrel shifter, when not optimizing for size. The current implementations of right shifts by a constant are optimal for code size, but at significant performance cost. By emitting an extra instruction or two, when not optimizing for size, we can improve performance (sometimes dramatically). [al]shrsi3 #5 Before 4 insns@12 cycles, after 5 insns@5 cycles Without -mswap [al]shrsi3 #29 Before 4 insns@60 cycles, after 5 insns@31 cycles With -mswap lshrsi3 #29 Before 4 insns@60 cycles, after 6 insns@16 cycles This patch has been minimally tested by building a cross-compiler to arc-linux hosted on x86_64-pc-linux-gnu where there are no new failures from "make -k check" in the compile-only tests. Ok for mainline (after 3rd-party testing)? 2024-07-11 Roger Sayle gcc/ChangeLog * config/arc/arc.cc (arc_split_ashr): When not optimizing for size; fully unroll ashr #5, on TARGET_SWAP for shifts between 19 and 29, perform ashr #16 using two instructions then recursively perform the remaining shift, and for shifts by odd amounts perform a single shift then the remainder of the shift using a loop doing two bits per iteration. (arc_split_lshr): Likewise. Thanks in advance, Roger diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc index 686de0ff2d5..b56e65d2d3e 100644 --- a/gcc/config/arc/arc.cc +++ b/gcc/config/arc/arc.cc @@ -4556,7 +4556,8 @@ arc_split_ashr (rtx *operands) if (CONST_INT_P (operands[2])) { int n = INTVAL (operands[2]) & 0x1f; - if (n <= 4) + if (n <= 4 + || (n == 5 && !optimize_function_for_size_p (cfun))) { if (n != 0) { @@ -4577,6 +4578,17 @@ arc_split_ashr (rtx *operands) emit_insn (gen_ashrsi3_cnt1 (operands[0], operands[0])); return; } + else if (n >= 19 && n <= 29 && TARGET_SWAP + && !optimize_function_for_size_p (cfun)) + { + emit_insn (gen_rotrsi2_cnt16 (operands[0], operands[1])); + emit_insn (gen_extendhisi2 (operands[0], + gen_lowpart (HImode, operands[0]))); + operands[1] = operands[0]; + operands[2] = GEN_INT (n - 16); + arc_split_ashr (operands); + return; + } else if (n == 30) { rtx tmp = gen_reg_rtx (SImode); @@ -4592,6 +4604,13 @@ arc_split_ashr (rtx *operands) emit_insn (gen_sbc (operands[0], operands[0], operands[0])); return; } + else if ((n & 1) != 0 && !optimize_function_for_size_p (cfun)) + { + emit_insn (gen_ashrsi3_cnt1 (operands[0], operands[1])); + emit_insn (gen_ashrsi3_loop (operands[0], operands[0], + GEN_INT (n - 1))); + return; + } } emit_insn (gen_ashrsi3_loop (operands[0], operands[1], operands[2])); @@ -4604,7 +4623,8 @@ arc_split_lshr (rtx *operands) if (CONST_INT_P (operands[2])) { int n = INTVAL (operands[2]) & 0x1f; - if (n <= 4) + if (n <= 4 + || (n == 5 && !optimize_function_for_size_p (cfun))) { if (n != 0) { @@ -4623,6 +4643,15 @@ arc_split_lshr (rtx *operands) emit_insn (gen_lshrsi3_cnt1 (operands[0], operands[0])); return; } + else if (n >= 20 && n <= 29 && TARGET_SWAP && TARGET_V2 + && !optimize_function_for_size_p (cfun)) + { + emit_insn (gen_lshrsi2_cnt16 (operands[0], operands[1])); + operands[1] = operands[0]; + operands[2] = GEN_INT (n - 16); + arc_split_lshr (operands); + return; + } else if (n == 30) { rtx tmp = gen_reg_rtx (SImode); @@ -4638,6 +4667,13 @@ arc_split_lshr (rtx *operands) emit_insn (gen_scc_ltu_cc_c (operands[0])); return; } + else if ((n & 1) != 0 && !optimize_function_for_size_p (cfun)) + { + emit_insn (gen_lshrsi3_cnt1 (operands[0], operands[1])); + emit_insn (gen_lshrsi3_loop (operands[0], operands[0], + GEN_INT (n - 1))); + return; + } } emit_insn (gen_lshrsi3_loop (operands[0], operands[1], operands[2]));