Message ID | 001601d86e75$13b5cc20$3b216460$@nextmovesoftware.com |
---|---|
State | New |
Headers | show |
Series | [x86] PR tree-optimization/105668: Provide vcond_mask_v1tiv1ti pattern. | expand |
On Mon, May 23, 2022 at 9:16 AM Roger Sayle <roger@nextmovesoftware.com> wrote: > > > This patch is an alternate/supplementary fix to PR tree-optimization/105668 > that provides a vcond_mask_v1titi optab/define_expand to the i386 backend. > An undocumented feature/bug of GCC's vectorization is that any target that > provides a vec_cmpeq<mode><mode> has to also provide a matching > vcond_mask<mode><mode>. This backend patch preserves the status quo, > rather than fixes the underlying problem. IIRC, I also hit this issue a while ago. I was under impression it was fixed in the meantime, but looks I was wrong. > One aspect of this clean-up is that ix86_expand_sse_movcc provides > fallback implementations using pand/pandn/por that effectively make > V2DImode and V1TImode vcond_mask available on any TARGET_SSE2, not > just TARGET_SSE4_2. This allows a simplification as V2DI mode can > be handled by using a VI_128 mode iterator instead of a VI124_128 > mode iterator, and instead this define_expand is effectively renamed > to provide a V1TImode vcond_mask expander (as V1TI isn't in VI_128). > > This patch has been tested on x86_64-pc-linux-gnu with make bootstrap > and make -k check, both with and without --target_board=unix{-m32} with > no new failures. The new test case is identical to the middle-end patch, > so if both patches are approved, this'll be committed only once. > Ok for mainline? OK. Thanks, Uros. > > > 2022-05-23 Roger Sayle <roger@nextmovesoftware.com> > > gcc/ChangeLog > PR tree-optimization/105668 > * config/i386/i386-expand.cc (ix86_expand_sse_movcc): Support > V1TImode, just like V2DImode. > * config/i386/sse.md (vcond_mask_<mode>Msseintvecmodelower>): > Use VI_128 mode iterator instead of VI124_128 to include V2DI. > (vcond_mask_v2div2di): Delete. > (vcond_mask_v1tiv1ti): New define_expand. > > gcc/testsuite/ChangeLog > PR tree-optimization/105668 > * gcc.target/i386/pr105668.c: New test case. > > > Roger > -- >
On Mon, May 23, 2022 at 10:00 AM Uros Bizjak <ubizjak@gmail.com> wrote: > > On Mon, May 23, 2022 at 9:16 AM Roger Sayle <roger@nextmovesoftware.com> wrote: > > > > > > This patch is an alternate/supplementary fix to PR tree-optimization/105668 > > that provides a vcond_mask_v1titi optab/define_expand to the i386 backend. > > An undocumented feature/bug of GCC's vectorization is that any target that > > provides a vec_cmpeq<mode><mode> has to also provide a matching > > vcond_mask<mode><mode>. This backend patch preserves the status quo, > > rather than fixes the underlying problem. > > IIRC, I also hit this issue a while ago. I was under impression it was > fixed in the meantime, but looks I was wrong. > > > One aspect of this clean-up is that ix86_expand_sse_movcc provides > > fallback implementations using pand/pandn/por that effectively make > > V2DImode and V1TImode vcond_mask available on any TARGET_SSE2, not > > just TARGET_SSE4_2. This allows a simplification as V2DI mode can > > be handled by using a VI_128 mode iterator instead of a VI124_128 > > mode iterator, and instead this define_expand is effectively renamed > > to provide a V1TImode vcond_mask expander (as V1TI isn't in VI_128). > > > > This patch has been tested on x86_64-pc-linux-gnu with make bootstrap > > and make -k check, both with and without --target_board=unix{-m32} with > > no new failures. The new test case is identical to the middle-end patch, > > so if both patches are approved, this'll be committed only once. > > Ok for mainline? > > OK. > > Thanks, > Uros. > > > > > > > 2022-05-23 Roger Sayle <roger@nextmovesoftware.com> > > > > gcc/ChangeLog > > PR tree-optimization/105668 > > * config/i386/i386-expand.cc (ix86_expand_sse_movcc): Support > > V1TImode, just like V2DImode. > > * config/i386/sse.md (vcond_mask_<mode>Msseintvecmodelower>): > > Use VI_128 mode iterator instead of VI124_128 to include V2DI. > > (vcond_mask_v2div2di): Delete. > > (vcond_mask_v1tiv1ti): New define_expand. > > > > gcc/testsuite/ChangeLog > > PR tree-optimization/105668 > > * gcc.target/i386/pr105668.c: New test case. diff --git a/gcc/testsuite/gcc.target/i386/pr105668.c b/gcc/testsuite/gcc.target/i386/pr105668.c new file mode 100644 index 0000000..359c2b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105668.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ Please use { target int128 } here. +/* { dg-options "-O -ftracer -fno-tree-fre" } */ + +typedef __int128 __attribute__((__vector_size__ (16))) V; > > > > Roger > > -- > >
On Mon, May 23, 2022 at 10:00 AM Uros Bizjak <ubizjak@gmail.com> wrote: > > On Mon, May 23, 2022 at 9:16 AM Roger Sayle <roger@nextmovesoftware.com> wrote: > > > > > > This patch is an alternate/supplementary fix to PR tree-optimization/105668 > > that provides a vcond_mask_v1titi optab/define_expand to the i386 backend. > > An undocumented feature/bug of GCC's vectorization is that any target that > > provides a vec_cmpeq<mode><mode> has to also provide a matching > > vcond_mask<mode><mode>. This backend patch preserves the status quo, > > rather than fixes the underlying problem. > > IIRC, I also hit this issue a while ago. I was under impression it was > fixed in the meantime, but looks I was wrong. It's generally prefered to have vec_cmp* and vcond_mask over vcond when the target will end up doing the compare and select in different instructions (IIRC the x86 ISA has no combined compare & select instructions). So it might be interesting to see if we can remove the vcond{,u,eq} expanders (and fill in missing vec_cmp and vcond_mask patterns). Richard. > > One aspect of this clean-up is that ix86_expand_sse_movcc provides > > fallback implementations using pand/pandn/por that effectively make > > V2DImode and V1TImode vcond_mask available on any TARGET_SSE2, not > > just TARGET_SSE4_2. This allows a simplification as V2DI mode can > > be handled by using a VI_128 mode iterator instead of a VI124_128 > > mode iterator, and instead this define_expand is effectively renamed > > to provide a V1TImode vcond_mask expander (as V1TI isn't in VI_128). > > > > This patch has been tested on x86_64-pc-linux-gnu with make bootstrap > > and make -k check, both with and without --target_board=unix{-m32} with > > no new failures. The new test case is identical to the middle-end patch, > > so if both patches are approved, this'll be committed only once. > > Ok for mainline? > > OK. > > Thanks, > Uros. > > > > > > > 2022-05-23 Roger Sayle <roger@nextmovesoftware.com> > > > > gcc/ChangeLog > > PR tree-optimization/105668 > > * config/i386/i386-expand.cc (ix86_expand_sse_movcc): Support > > V1TImode, just like V2DImode. > > * config/i386/sse.md (vcond_mask_<mode>Msseintvecmodelower>): > > Use VI_128 mode iterator instead of VI124_128 to include V2DI. > > (vcond_mask_v2div2di): Delete. > > (vcond_mask_v1tiv1ti): New define_expand. > > > > gcc/testsuite/ChangeLog > > PR tree-optimization/105668 > > * gcc.target/i386/pr105668.c: New test case. > > > > > > Roger > > -- > >
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 1460bcc..e3bd661 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -4026,6 +4026,7 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) case E_V8HFmode: case E_V4SImode: case E_V2DImode: + case E_V1TImode: if (TARGET_SSE4_1) { gen = gen_sse4_1_pblendvb; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 191371b..f261ff6 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4579,10 +4579,10 @@ }) (define_expand "vcond_mask_<mode><sseintvecmodelower>" - [(set (match_operand:VI124_128 0 "register_operand") - (vec_merge:VI124_128 - (match_operand:VI124_128 1 "vector_operand") - (match_operand:VI124_128 2 "nonimm_or_0_operand") + [(set (match_operand:VI_128 0 "register_operand") + (vec_merge:VI_128 + (match_operand:VI_128 1 "vector_operand") + (match_operand:VI_128 2 "nonimm_or_0_operand") (match_operand:<sseintvecmode> 3 "register_operand")))] "TARGET_SSE2" { @@ -4591,13 +4591,13 @@ DONE; }) -(define_expand "vcond_mask_v2div2di" - [(set (match_operand:V2DI 0 "register_operand") - (vec_merge:V2DI - (match_operand:V2DI 1 "vector_operand") - (match_operand:V2DI 2 "nonimm_or_0_operand") - (match_operand:V2DI 3 "register_operand")))] - "TARGET_SSE4_2" +(define_expand "vcond_mask_v1tiv1ti" + [(set (match_operand:V1TI 0 "register_operand") + (vec_merge:V1TI + (match_operand:V1TI 1 "vector_operand") + (match_operand:V1TI 2 "nonimm_or_0_operand") + (match_operand:V1TI 3 "register_operand")))] + "TARGET_SSE2" { ix86_expand_sse_movcc (operands[0], operands[3], operands[1], operands[2]); diff --git a/gcc/testsuite/gcc.target/i386/pr105668.c b/gcc/testsuite/gcc.target/i386/pr105668.c new file mode 100644 index 0000000..359c2b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105668.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O -ftracer -fno-tree-fre" } */ + +typedef __int128 __attribute__((__vector_size__ (16))) V; + +int i; + +V +foo (_Complex float f) +{ + (void) __builtin_atanhf (i); + V v = i != (V) { }; + i ^= f && 8; + v %= 5; + return v; +}