From patchwork Mon Jun 18 03:11:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joey Ye X-Patchwork-Id: 165381 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 46FD9B700D for ; Mon, 18 Jun 2012 13:11:03 +1000 (EST) Comment: DKIM? See http://www.dkim.org DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=gcc.gnu.org; s=default; x=1340593864; h=Comment: DomainKey-Signature:Received:Received:Received:Received:Received: From:To:Subject:Date:Message-ID:MIME-Version:Content-Type: Content-Transfer-Encoding:Mailing-List:Precedence:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:Sender: Delivered-To; bh=Kz80Z2Up2XvlsNocmjZBkZ2++74=; b=UjSmZXzocxovnqk VGI4bha2Z2OXicGXlC2L86geE14oCZEgebF+/aDRGfF0SuAv/2+17c4BSMChxIGw lxfECMJrlHr9blYOnupp1y0Szc7XniQ+cJctavVAD2pREUUASqcII66SfSWxuMVY 5kaR+KvNYiGq71qNjlOj3uzWR0zA= Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:From:To:Subject:Date:Message-ID:MIME-Version:X-MC-Unique:Content-Type:Content-Transfer-Encoding:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=xvWV4P54JGkV9MI5SkYt2u/0kzNvZ5CYEpHiWXFqQk1DDCKGc6q7LdMW8QXTon OwdshDcWRWtGKZ/vkF/JlEw5jOXW7rrRKZApDcyCZ5+aw0NGrSC8oAhD8sa3AL3S kX4yvTQSPXFzbHWHDEw+d5CELKO2/4/lZEZICPMhzphac=; Received: (qmail 28177 invoked by alias); 18 Jun 2012 03:11:00 -0000 Received: (qmail 28168 invoked by uid 22791); 18 Jun 2012 03:10:58 -0000 X-SWARE-Spam-Status: No, hits=-0.2 required=5.0 tests=AWL, BAYES_40, KHOP_RCVD_UNTRUST, MSGID_MULTIPLE_AT, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_NO, RCVD_IN_HOSTKARMA_YE X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 18 Jun 2012 03:10:45 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 18 Jun 2012 04:10:43 +0100 Received: from E103005 ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 18 Jun 2012 04:11:22 +0100 From: "Joey Ye" To: "GCC Patches" Subject: [4.6][ARM] Backport fix PR48126 Date: Mon, 18 Jun 2012 11:11:03 +0800 Message-ID: <000a01cd4d00$006b6770$01423650$@ye@arm.com> MIME-Version: 1.0 X-MC-Unique: 112061804104300201 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org OK for 4.6? 2012-06-18 Joey Ye Backport from mainline 2011-10-14 David Alan Gilbert PR target/48126 * config/arm/arm.c (arm_output_sync_loop): Move label before barrier. Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 188331) +++ gcc/config/arm/arm.c (working copy) @@ -23423,8 +23423,11 @@ } } + /* Note: label is before barrier so that in cmp failure case we still get + a barrier to stop subsequent loads floating upwards past the ldrex + PR target/48126. */ + arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); arm_process_output_memory_barrier (emit, NULL); - arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); } static rtx Index: gcc/config/arm/arm.h =================================================================== --- gcc/config/arm/arm.h (revision 188331) +++ gcc/config/arm/arm.h (working copy) @@ -294,7 +294,8 @@ #define TARGET_HAVE_DMB (arm_arch7) /* Nonzero if this chip implements a memory barrier via CP15. */ -#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB) +#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ + && ! TARGET_THUMB1) /* Nonzero if this chip implements a memory barrier instruction. */ #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)