From patchwork Wed Dec 16 09:11:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 557362 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9E6141402C4 for ; Wed, 16 Dec 2015 20:11:20 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=sWfY315V; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=U+gtOahRpUNj42B7 wBeIzXxtBo2Sr6OCnKdmSOpfa4P8+mNuXHFPumIJhVMhikHaCDqdHHHsYEbVd6eL aL+BKC7ArLN4/O4C+6Zhn2crNYjCYgGc4Tj0Uhj/BAt9lJDTRqqNNQ/OBlkDTiN6 rLSXElTFG+8AK6oBQMUlilrVI4s= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=wHXlMPc3LJi/dpZ3PsI/I6 xJds0=; b=sWfY315VUqUrSdfeQLGpjjQZZpFLPQcoPsn0IOlgt7SKJ2H0Pqa/WK ozpmvs02/C2gVeUSJJKdoBiTjOT9bmJ9Gj1TJPwbZG1Xs6aY23MgoSkE3gdxCVkZ eJAjiV12eDXFiK2IWg9grHciP1h1Es+CFT57RzoST2WOS508J5rkY= Received: (qmail 81807 invoked by alias); 16 Dec 2015 09:11:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 81793 invoked by uid 89); 16 Dec 2015 09:11:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 16 Dec 2015 09:11:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 164C7600; Wed, 16 Dec 2015 01:10:44 -0800 (PST) Received: from SHAWIN202 (unknown [10.164.12.31]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A87473F21A; Wed, 16 Dec 2015 01:11:06 -0800 (PST) From: "Thomas Preud'homme" To: , "'Richard Earnshaw'" , "Ramana Radhakrishnan" , "Kyrylo Tkachov" Subject: [PATCH, ARM] Fix gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0 Date: Wed, 16 Dec 2015 17:11:03 +0800 Message-ID: <000001d137e1$b2956700$17c03500$@foss.arm.com> MIME-Version: 1.0 During reorg pass, thumb1_reorg () is tasked with rewriting mov rd, rn to subs rd, rn, 0 to avoid a comparison against 0 instruction before doing a conditional branch based on it. The actual avoiding of cmp is done in cbranchsi4_insn instruction C output template. When the condition is met, the source register (rn) is also propagated into the comparison in place the destination register (rd). However, right now thumb1_reorg () only look for a mov followed by a cbranchsi but does not check whether the comparison in cbranchsi is against the constant 0. This is not safe because a non clobbering instruction could exist between the mov and the comparison that modifies the source register. This is what happens here with a post increment of the source register after the mov, which skip the &a[i] == &a[1] comparison for iteration i == 1. This patch fixes the issue by checking that the comparison is against constant 0. ChangeLog entry is as follow: *** gcc/ChangeLog *** 2015-12-07 Thomas Preud'homme * config/arm/arm.c (thumb1_reorg): Check that the comparison is against the constant 0. Testsuite shows no regression when run for arm-none-eabi with -mcpu=cortex-m0 -mthumb Is this ok for trunk? Best regards, Thomas diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 42bf272..49c0a06 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -17195,7 +17195,7 @@ thumb1_reorg (void) FOR_EACH_BB_FN (bb, cfun) { rtx dest, src; - rtx pat, op0, set = NULL; + rtx cmp, op0, op1, set = NULL; rtx_insn *prev, *insn = BB_END (bb); bool insn_clobbered = false; @@ -17208,8 +17208,13 @@ thumb1_reorg (void) continue; /* Get the register with which we are comparing. */ - pat = PATTERN (insn); - op0 = XEXP (XEXP (SET_SRC (pat), 0), 0); + cmp = XEXP (SET_SRC (PATTERN (insn)), 0); + op0 = XEXP (cmp, 0); + op1 = XEXP (cmp, 1); + + /* Check that comparison is against ZERO. */ + if (!CONST_INT_P (op1) || INTVAL (op1) != 0) + continue; /* Find the first flag setting insn before INSN in basic block BB. */ gcc_assert (insn != BB_HEAD (bb)); @@ -17249,7 +17254,7 @@ thumb1_reorg (void) PATTERN (prev) = gen_rtx_SET (dest, src); INSN_CODE (prev) = -1; /* Set test register in INSN to dest. */ - XEXP (XEXP (SET_SRC (pat), 0), 0) = copy_rtx (dest); + XEXP (cmp, 0) = copy_rtx (dest); INSN_CODE (insn) = -1; } }