From patchwork Mon Aug 4 09:09:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenqiang Chen X-Patchwork-Id: 376174 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C3A31140096 for ; Mon, 4 Aug 2014 19:10:29 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:references:in-reply-to:subject:date:message-id :mime-version:content-type:content-transfer-encoding; q=dns; s= default; b=o19+LOsBrUo+OI81AECm8LLuNhzw1gsSMmTejqByU3iMF1QXqPXhZ YqvdzxZBARg3Xp700QX8h1hzm5suKzK8PMO8N7hyi8T7bEVmtCri+Wj/C2PymOM3 I5zxAZJnBJgfKaEXurV4MltpuaA1uUVwi4rGtrOqftswoYVyJTjm5w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:references:in-reply-to:subject:date:message-id :mime-version:content-type:content-transfer-encoding; s=default; bh=FavYbaOE1dI8w9lHR+3mPjlkhTE=; b=blOnwUtk5PjHnzs41E2x/rbsuEkA 74vMj72De2kL/8dIS/wVQza81j5wXUNnEVz8KXznY8yURiCbQ7RYRo1y8UFwF/s7 ktjdZWoyOnsKHWVtCcWjuURJ2zoQMPlRb/p1nQnGfH03Y/0m1mC2un3mPSDdFHpE DMxBmdPEeBgCR4M= Received: (qmail 26263 invoked by alias); 4 Aug 2014 09:10:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 26213 invoked by uid 89); 4 Aug 2014 09:10:18 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 04 Aug 2014 09:10:12 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 04 Aug 2014 10:10:10 +0100 Received: from shawin003 ([10.164.2.37]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 Aug 2014 10:10:08 +0100 From: "Zhenqiang Chen" To: "'Bin.Cheng'" Cc: "gcc-patches List" References: <000001cfafad$5de00840$19a018c0$@arm.com> In-Reply-To: Subject: RE: [PATCH, ivopt] Try aligned offset when get_address_cost Date: Mon, 4 Aug 2014 17:09:42 +0800 Message-ID: <000001cfafc3$d5372c00$7fa58400$@arm.com> MIME-Version: 1.0 X-MC-Unique: 114080410101000501 X-IsSubscribed: yes > -----Original Message----- > From: Bin.Cheng [mailto:amker.cheng@gmail.com] > Sent: Monday, August 04, 2014 4:41 PM > To: Zhenqiang Chen > Cc: gcc-patches List > Subject: Re: [PATCH, ivopt] Try aligned offset when get_address_cost > > On Mon, Aug 4, 2014 at 2:28 PM, Zhenqiang Chen > wrote: > > Hi, > > > > For some TARGET, like ARM THUMB1, the offset in load/store should be > > nature aligned. But in function get_address_cost, when computing > > max_offset, it only tries byte-aligned offsets: > > > > ((unsigned HOST_WIDE_INT) 1 << i) - 1 > > > > which can not meet thumb_legitimate_offset_p check called from > > thumb1_legitimate_address_p for HImode and SImode. > > > > The patch adds additional try for aligned offset: > > > > ((unsigned HOST_WIDE_INT) 1 << i) - GET_MODE_SIZE (address_mode). > > > > Bootstrap and no make check regression on X86-64. > > No make check regression on qemu for Cortex-m0 and Cortex-m3. > > For Cortex-m0, no performance changes with coremark and dhrystone. > > Coremark code size is ~0.44 smaller. And eembcv2 code size is ~0.22 > > smaller. CSiBE code size is ~0.05% smaller. > > > > OK for trunk? > > > > Thanks! > > -Zhenqiang > > > > ChangeLog > > 2014-08-04 Zhenqiang Chen > > > > * tree-ssa-loop-ivopts.c (get_address_cost): Try aligned offset. > > > > testsuite/ChangeLog: > > 2014-08-04 Zhenqiang Chen > > > > * gcc.target/arm/get_address_cost_aligned_max_offset.c: New test. > > > > diff --git a/gcc/tree-ssa-loop-ivopts.c b/gcc/tree-ssa-loop-ivopts.c > > index 3b4a6cd..562122a 100644 > > --- a/gcc/tree-ssa-loop-ivopts.c > > +++ b/gcc/tree-ssa-loop-ivopts.c > > @@ -3308,6 +3308,18 @@ get_address_cost (bool symbol_present, bool > > var_present, > > XEXP (addr, 1) = gen_int_mode (off, address_mode); > > if (memory_address_addr_space_p (mem_mode, addr, as)) > > break; > > + /* For some TARGET, like ARM THUMB1, the offset should be nature > > + aligned. Try an aligned offset if address_mode is not QImode. > > */ > > + off = (address_mode == QImode) > > + ? 0 > > + : ((unsigned HOST_WIDE_INT) 1 << i) > > + - GET_MODE_SIZE (address_mode); > > + if (off > 0) > > + { > > + XEXP (addr, 1) = gen_int_mode (off, address_mode); > > + if (memory_address_addr_space_p (mem_mode, addr, as)) > > + break; > > + } > Hi, Why not just check "address_mode != QImode"? Set off to 0 then check it > seems unnecessary. Thanks for the comments. ((unsigned HOST_WIDE_INT) 1 << i) - GET_MODE_SIZE (address_mode) might be a negative value except QImode. A negative value can not be max_offset. So we do not need to check it. For QImode, "((unsigned HOST_WIDE_INT) 1 << i) - GET_MODE_SIZE (address_mode)" == "((unsigned HOST_WIDE_INT) 1 << i) - 1". It is already checked. So no need to check it again. I think the compiler can optimize the patch like if (i == -1) off = 0; > Thanks, > bin > > } > > if (i == -1) > > off = 0; > > diff --git > > a/gcc/testsuite/gcc.target/arm/get_address_cost_aligned_max_offset.c > > b/gcc/testsuite/gcc.target/arm/get_address_cost_aligned_max_offset.c > > new file mode 100644 > > index 0000000..cc3e2f7 > > --- /dev/null > > +++ > b/gcc/testsuite/gcc.target/arm/get_address_cost_aligned_max_offset > > +++ .c > > @@ -0,0 +1,28 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-mthumb -O2" } */ > > +/* { dg-require-effective-target arm_thumb1_ok } */ > > + > > +unsigned int > > +test (const short p16[6 * 64]) > > +{ > > + unsigned int i = 6; > > + unsigned int ret = 0; > > + > > + do > > + { > > + unsigned long long *p64 = (unsigned long long*) p16; > > + unsigned int *p32 = (unsigned int*) p16; > > + ret += ret; > > + if (p16[1] || p32[1]) > > + ret++; > > + else if (p64[1] | p64[2] | p64[3]) > > + ret++; > > + p16 += 64; > > + i--; > > + } while (i != 0); > > + > > + return ret; > > +} > > + > > +/* { dg-final { scan-assembler-not "#22" } } */ > > +/* { dg-final { scan-assembler-not "#14" } } */ > > > > > > diff --git a/gcc/tree-ssa-loop-ivopts.c b/gcc/tree-ssa-loop-ivopts.c index 3b4a6cd..213598a 100644 --- a/gcc/tree-ssa-loop-ivopts.c +++ b/gcc/tree-ssa-loop-ivopts.c @@ -3308,6 +3308,19 @@ get_address_cost (bool symbol_present, bool var_present, XEXP (addr, 1) = gen_int_mode (off, address_mode); if (memory_address_addr_space_p (mem_mode, addr, as)) break; + /* For some TARGET, like ARM THUMB1, the offset should be nature + aligned. Try an aligned offset if address_mode is not QImode. */ + if (address_mode != QImode) + { + off = ((unsigned HOST_WIDE_INT) 1 << i) + - GET_MODE_SIZE (address_mode); + if (off > 0) + { + XEXP (addr, 1) = gen_int_mode (off, address_mode); + if (memory_address_addr_space_p (mem_mode, addr, as)) + break; + } + } }