Show patches with: Submitter = Roger Sayle       |    State = Action Required       |    Archived = No       |   474 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
Replace lra-spill.cc's return_regno_p with return_reg_p. Replace lra-spill.cc's return_regno_p with return_reg_p. - - - - --- 2023-07-22 Roger Sayle New
[x86] Use QImode for offsets in zero_extract/sign_extract in i386.md [x86] Use QImode for offsets in zero_extract/sign_extract in i386.md - - - - --- 2023-07-22 Roger Sayle New
[x86] Don't use insvti_{high, low}part with -O0 (for compile-time). [x86] Don't use insvti_{high, low}part with -O0 (for compile-time). - - - - --- 2023-07-22 Roger Sayle New
PR c/110699: Defend against error_mark_node in gimplify.cc. PR c/110699: Defend against error_mark_node in gimplify.cc. - - - - --- 2023-07-19 Roger Sayle New
[x86_64] More TImode parameter passing improvements. [x86_64] More TImode parameter passing improvements. - - - - --- 2023-07-19 Roger Sayle New
Fix bootstrap failure (with g++ 4.8.5) in tree-if-conv.cc. Fix bootstrap failure (with g++ 4.8.5) in tree-if-conv.cc. - - - - --- 2023-07-14 Roger Sayle New
[x86] PR target/110588: Add *bt<mode>_setncqi_2 to generate btl [x86] PR target/110588: Add *bt<mode>_setncqi_2 to generate btl - - - - --- 2023-07-13 Roger Sayle New
[x86_64] Improved insv of DImode/DFmode {high, low}parts into TImode. [x86_64] Improved insv of DImode/DFmode {high, low}parts into TImode. - - - - --- 2023-07-13 Roger Sayle New
[x86] Fix FAIL of gcc.target/i386/pr91681-1.c [x86] Fix FAIL of gcc.target/i386/pr91681-1.c - - - - --- 2023-07-11 Roger Sayle New
[x86] PR target/110598: Fix rega = 0; rega ^= rega regression. [x86] PR target/110598: Fix rega = 0; rega ^= rega regression. - - - - --- 2023-07-11 Roger Sayle New
[X86] Add new insvti_lowpart_1 and insvdi_lowpart_1 patterns. [X86] Add new insvti_lowpart_1 and insvdi_lowpart_1 patterns. - - - - --- 2023-07-09 Roger Sayle New
[x86] Add AVX512 support for STV of SI/DImode rotation by constant. [x86] Add AVX512 support for STV of SI/DImode rotation by constant. - - - - --- 2023-07-09 Roger Sayle New
[x86_64] Improve __int128 argument passing (in ix86_expand_move). [x86_64] Improve __int128 argument passing (in ix86_expand_move). - - - - --- 2023-07-06 Roger Sayle New
[Committed] Handle COPYSIGN in dwarf2out.cc'd mem_loc_descriptor [Committed] Handle COPYSIGN in dwarf2out.cc'd mem_loc_descriptor - - - - --- 2023-07-06 Roger Sayle New
[x86] Add STV support for DImode and SImode rotations by constant. [x86] Add STV support for DImode and SImode rotations by constant. - - - - --- 2023-06-30 Roger Sayle New
[Committed] Add -mmove-max=128 -mstore-max=128 to pieces-memcmp-2.c [Committed] Add -mmove-max=128 -mstore-max=128 to pieces-memcmp-2.c - - - - --- 2023-06-29 Roger Sayle New
[x86] Tweak ix86_expand_int_compare to use PTEST for vector equality. [x86] Tweak ix86_expand_int_compare to use PTEST for vector equality. - - - - --- 2023-06-27 Roger Sayle New
[x86] Fix FAIL of gcc.target/i386/pr78794.c on ia32. [x86] Fix FAIL of gcc.target/i386/pr78794.c on ia32. - - - - --- 2023-06-27 Roger Sayle New
[x86] Add cbranchti4 pattern to i386.md (for -m32 compare_by_pieces). [x86] Add cbranchti4 pattern to i386.md (for -m32 compare_by_pieces). - - - - --- 2023-06-27 Roger Sayle New
[x86_PATCH] New *ashl<dwi3>_doubleword_highpart define_insn_and_split. [x86_PATCH] New *ashl<dwi3>_doubleword_highpart define_insn_and_split. - - - - --- 2023-06-24 Roger Sayle New
[x86_64] Handle SUBREG conversions in TImode STV (for ptest). [x86_64] Handle SUBREG conversions in TImode STV (for ptest). - - - - --- 2023-06-24 Roger Sayle New
[RFC] Workaround LRA reload issue with SUBREGs in SET_DEST. [RFC] Workaround LRA reload issue with SUBREGs in SET_DEST. - - - - --- 2023-06-18 Roger Sayle New
[x86] Refactor new ix86_expand_carry to set the carry flag. [x86] Refactor new ix86_expand_carry to set the carry flag. - - - - --- 2023-06-18 Roger Sayle New
Improved SUBREG simplifications in simplify-rtx.cc's simplify_subreg. Improved SUBREG simplifications in simplify-rtx.cc's simplify_subreg. - - - - --- 2023-06-18 Roger Sayle New
[x86] Add alternate representation for {and,or,xor}b %ah,%dh. [x86] Add alternate representation for {and,or,xor}b %ah,%dh. - - - - --- 2023-06-18 Roger Sayle New
[x86] Standardize shift amount constants as QImode. [x86] Standardize shift amount constants as QImode. - - - - --- 2023-06-18 Roger Sayle New
[x86_64] Two minor tweaks to ix86_expand_move. [x86_64] Two minor tweaks to ix86_expand_move. - - - - --- 2023-06-16 Roger Sayle New
[x86] Convert ptestz of pandn into ptestc. [x86] Convert ptestz of pandn into ptestc. - - - - --- 2023-06-13 Roger Sayle New
New finish_compare_by_pieces target hook (for x86). New finish_compare_by_pieces target hook (for x86). - - - - --- 2023-06-12 Roger Sayle New
Avoid duplicate vector initializations during RTL expansion. Avoid duplicate vector initializations during RTL expansion. - - - - --- 2023-06-11 Roger Sayle New
[13] PR target/109973: CCZmode and CCCmode variants of [v]ptest. [13] PR target/109973: CCZmode and CCCmode variants of [v]ptest. - - - - --- 2023-06-10 Roger Sayle New
[nvptx] Update nvptx's bitrev<mode>2 pattern to use BITREVERSE rtx. [nvptx] Update nvptx's bitrev<mode>2 pattern to use BITREVERSE rtx. - - - - --- 2023-06-07 Roger Sayle New
[Committed] Bug fix to new wi::bitreverse_large function. [Committed] Bug fix to new wi::bitreverse_large function. - - - - --- 2023-06-07 Roger Sayle New
[x86] PR target/31985: Improve memory operand use with doubleword add. [x86] PR target/31985: Improve memory operand use with doubleword add. - - - - --- 2023-06-06 Roger Sayle New
[x86_64] PR target/110104: Missing peephole2 for addcarry<mode>. [x86_64] PR target/110104: Missing peephole2 for addcarry<mode>. - - - - --- 2023-06-06 Roger Sayle New
[x86] Add support for stc, clc and cmc instructions in i386.md [x86] Add support for stc, clc and cmc instructions in i386.md - - - - --- 2023-06-03 Roger Sayle New
[x86_64] PR target/110083: Fix-up REG_EQUAL notes on COMPARE in STV. [x86_64] PR target/110083: Fix-up REG_EQUAL notes on COMPARE in STV. - - - - --- 2023-06-03 Roger Sayle New
New wi::bitreverse function. New wi::bitreverse function. - - - - --- 2023-06-02 Roger Sayle New
[x86_64] PR target/109973: CCZmode and CCCmode variants of [v]ptest. [x86_64] PR target/109973: CCZmode and CCCmode variants of [v]ptest. - - - - --- 2023-05-29 Roger Sayle New
Refactor wi::bswap as a function (instead of a method). Refactor wi::bswap as a function (instead of a method). - - - - --- 2023-05-28 Roger Sayle New
PR target/107172: Avoid "unusual" MODE_CC comparisons in simplify-rtx.cc PR target/107172: Avoid "unusual" MODE_CC comparisons in simplify-rtx.cc - - - - --- 2023-05-26 Roger Sayle New
Replace a HWI_COMPUTABLE_MODE_P with wide-int in simplify-rtx.cc. Replace a HWI_COMPUTABLE_MODE_P with wide-int in simplify-rtx.cc. - - - - --- 2023-05-26 Roger Sayle New
[i386] A minor code clean-up: Use NULL_RTX instead of nullptr [i386] A minor code clean-up: Use NULL_RTX instead of nullptr - - - - --- 2023-05-24 Roger Sayle New
PR middle-end/109840: Preserve popcount/parity type in match.pd. PR middle-end/109840: Preserve popcount/parity type in match.pd. - - - - --- 2023-05-23 Roger Sayle New
[x86_64] PR middle-end/109766: Prevent cprop_hardreg bloating code with -Os. [x86_64] PR middle-end/109766: Prevent cprop_hardreg bloating code with -Os. - - - - --- 2023-05-11 Roger Sayle New
match.pd: Simplify popcount(X&Y)+popcount(X|Y) as popcount(X)+popcount(Y) match.pd: Simplify popcount(X&Y)+popcount(X|Y) as popcount(X)+popcount(Y) - - - - --- 2023-05-10 Roger Sayle New
[x86_64] Use [(const_int 0)] idiom consistently in i386.md [x86_64] Use [(const_int 0)] idiom consistently in i386.md - - - - --- 2023-05-10 Roger Sayle New
[take,#3] match.pd: Simplify popcount/parity of bswap/rotate. [take,#3] match.pd: Simplify popcount/parity of bswap/rotate. - - - - --- 2023-05-10 Roger Sayle New
[libgcc] Add bit reversal functions __bitrev[qhsd]i2. [libgcc] Add bit reversal functions __bitrev[qhsd]i2. - - - - --- 2023-05-06 Roger Sayle New
Add RTX codes for BITREVERSE and COPYSIGN. Add RTX codes for BITREVERSE and COPYSIGN. - - - - --- 2023-05-06 Roger Sayle New
nvptx: Add suppport for __builtin_nvptx_brev instrinsic. nvptx: Add suppport for __builtin_nvptx_brev instrinsic. - - - - --- 2023-05-06 Roger Sayle New
[x86_64] Introduce insvti_highpart define_insn_and_split. [x86_64] Introduce insvti_highpart define_insn_and_split. - - - - --- 2023-05-06 Roger Sayle New
Don't call emit_clobber in lower-subreg.cc's resolve_simple_move. Don't call emit_clobber in lower-subreg.cc's resolve_simple_move. - - - - --- 2023-05-06 Roger Sayle New
[Committed] Update xstormy16's neghi2 pattern to not clobber the carry flag. [Committed] Update xstormy16's neghi2 pattern to not clobber the carry flag. - - - - --- 2023-04-30 Roger Sayle New
[xstormy16] Efficient HImode rotate left by a single bit. [xstormy16] Efficient HImode rotate left by a single bit. - - - - --- 2023-04-29 Roger Sayle New
[xstormy16] Recognize/support swpn (swap nibbles) instruction. [xstormy16] Recognize/support swpn (swap nibbles) instruction. - - - - --- 2023-04-29 Roger Sayle New
Synchronize include/ctf.h with upstream binutils/libctf. Synchronize include/ctf.h with upstream binutils/libctf. - - - - --- 2023-04-27 Roger Sayle New
[xstormy16] Add support for byte and word swapping instructions. [xstormy16] Add support for byte and word swapping instructions. - - - - --- 2023-04-25 Roger Sayle New
[Committed] Correct zeroextendqihi2 insn length regression on xstormy16. [Committed] Correct zeroextendqihi2 insn length regression on xstormy16. - - - - --- 2023-04-25 Roger Sayle New
PR rtl-optimization/109476: Use ZERO_EXTEND instead of zeroing a SUBREG. PR rtl-optimization/109476: Use ZERO_EXTEND instead of zeroing a SUBREG. - - - - --- 2023-04-23 Roger Sayle New
[xstormy16] Add extendhisi2 and zero_extendhisi2 patterns to stormy16.md [xstormy16] Add extendhisi2 and zero_extendhisi2 patterns to stormy16.md - - - - --- 2023-04-22 Roger Sayle New
[xstormy16] Improved SImode shifts by two bits. [xstormy16] Improved SImode shifts by two bits. - - - - --- 2023-04-22 Roger Sayle New
[xstormy16] Update xstormy16_rtx_costs. [xstormy16] Update xstormy16_rtx_costs. - - - - --- 2023-04-22 Roger Sayle New
[Committed] New test case gcc.target/avr/pr54816.c [Committed] New test case gcc.target/avr/pr54816.c - - - - --- 2023-04-16 Roger Sayle New
PR middle-end/109031: Fix final value replacement from narrower IVs. PR middle-end/109031: Fix final value replacement from narrower IVs. - - - - --- 2023-03-12 Roger Sayle New
PR rtl-optimization/106594: Preserve zero_extend in combine when cheap. PR rtl-optimization/106594: Preserve zero_extend in combine when cheap. - - - - --- 2023-03-04 Roger Sayle New
[DOC] Document the VEC_PERM_EXPR tree code (and minor clean-ups). [DOC] Document the VEC_PERM_EXPR tree code (and minor clean-ups). - - - - --- 2023-02-04 Roger Sayle New
PR rtl-optimization/106421: ICE in bypass_block from non-local goto. PR rtl-optimization/106421: ICE in bypass_block from non-local goto. - - - - --- 2023-01-09 Roger Sayle New
[x86] PR rtl-optimization/107991: peephole2 to tweak register allocation. [x86] PR rtl-optimization/107991: peephole2 to tweak register allocation. - - - - --- 2023-01-09 Roger Sayle New
[nvptx] Correct pattern for popcountdi2 insn in nvptx.md. [nvptx] Correct pattern for popcountdi2 insn in nvptx.md. - - - - --- 2023-01-09 Roger Sayle New
[x86_64] Introduce insvti_highpart define_insn_and_split. [x86_64] Introduce insvti_highpart define_insn_and_split. - - - - --- 2023-01-05 Roger Sayle New
PR tree-optimization/92342: Optimize b & -(a==c) in match.pd PR tree-optimization/92342: Optimize b & -(a==c) in match.pd - - - - --- 2023-01-03 Roger Sayle New
[x86] Improve ix86_expand_int_movcc to allow condition (mask) sharing. [x86] Improve ix86_expand_int_movcc to allow condition (mask) sharing. - - - - --- 2023-01-02 Roger Sayle New
[x86] PR target/108229: A minor STV compute_convert_gain tweak. [x86] PR target/108229: A minor STV compute_convert_gain tweak. - - - - --- 2023-01-01 Roger Sayle New
Fix RTL simplifications of FFS, POPCOUNT and PARITY. Fix RTL simplifications of FFS, POPCOUNT and PARITY. - - - - --- 2023-01-01 Roger Sayle New
[x86] Provide zero_extend versions/variants of several patterns. [x86] Provide zero_extend versions/variants of several patterns. - - - - --- 2022-12-28 Roger Sayle New
[x86_64] Add post-reload splitter for extendditi2. [x86_64] Add post-reload splitter for extendditi2. - - - - --- 2022-12-28 Roger Sayle New
[x86] Use ix86_expand_clear in ix86_split_ashl. [x86] Use ix86_expand_clear in ix86_split_ashl. - - - - --- 2022-12-28 Roger Sayle New
[Committed] Tweak new gcc.target/i386/pr107548-1.c for -march=cascadelake. [Committed] Tweak new gcc.target/i386/pr107548-1.c for -march=cascadelake. - - - - --- 2022-12-24 Roger Sayle New
[x86] Use movss/movsd to implement V4SI/V2DI VEC_PERM. [x86] Use movss/movsd to implement V4SI/V2DI VEC_PERM. - - - - --- 2022-12-23 Roger Sayle New
[x86] PR target/107548: Handle vec_select in STV. [x86] PR target/107548: Handle vec_select in STV. - - - - --- 2022-12-22 Roger Sayle New
[x86] PR target/106933: Limit TImode STV to SSA-like def-use chains. [x86] PR target/106933: Limit TImode STV to SSA-like def-use chains. - - - - --- 2022-12-22 Roger Sayle New
Optimize (X<<C)+(Y<<C) as (X+Y)<<C for signed addition. Optimize (X<<C)+(Y<<C) as (X+Y)<<C for signed addition. - - - - --- 2022-09-13 Roger Sayle New
PR tree-optimization/71343: Value number X<<2 as X*4. PR tree-optimization/71343: Value number X<<2 as X*4. - - - - --- 2022-09-13 Roger Sayle New
PR target/106877: Robustify reg-stack to malformed asm. PR target/106877: Robustify reg-stack to malformed asm. - - - - --- 2022-09-13 Roger Sayle New
PR rtl-optimization/106594: Preserve zero_extend when cheap. PR rtl-optimization/106594: Preserve zero_extend when cheap. - - - - --- 2022-09-11 Roger Sayle New
[Committed] PR target/106640: Fix use of XINT in TImode compute_convert_gain. [Committed] PR target/106640: Fix use of XINT in TImode compute_convert_gain. - - - - --- 2022-08-17 Roger Sayle New
[x86_64] Support shifts and rotates by integer constants in TImode STV. [x86_64] Support shifts and rotates by integer constants in TImode STV. - - - - --- 2022-08-15 Roger Sayle New
[take,#2] PR tree-optimization/71343: Optimize (X<<C)&(Y<<C) as (X&Y)<<C. [take,#2] PR tree-optimization/71343: Optimize (X<<C)&(Y<<C) as (X&Y)<<C. - - - - --- 2022-08-12 Roger Sayle New
[x86,take,#2] Move V1TI shift/rotate lowering from expand to pre-reload split. [x86,take,#2] Move V1TI shift/rotate lowering from expand to pre-reload split. - - - - --- 2022-08-12 Roger Sayle New
[x86] PR target/106577: force_reg may clobber operands during split. [x86] PR target/106577: force_reg may clobber operands during split. - - - - --- 2022-08-12 Roger Sayle New
[Committed] PR other/106575: Use "signed char" in new fold-eqandshift-4.c [Committed] PR other/106575: Use "signed char" in new fold-eqandshift-4.c - - - - --- 2022-08-10 Roger Sayle New
[x86_64] Use PTEST to perform AND in TImode STV of (A & B) != 0. [x86_64] Use PTEST to perform AND in TImode STV of (A & B) != 0. - - - - --- 2022-08-09 Roger Sayle New
PR tree-optimization/64992: (B << 2) != 0 is B when B is Boolean. PR tree-optimization/64992: (B << 2) != 0 is B when B is Boolean. - - - - --- 2022-08-08 Roger Sayle New
PR tree-optimization/71343: Optimize (X<<C)&(Y<<C) as (X&Y)<<C. PR tree-optimization/71343: Optimize (X<<C)&(Y<<C) as (X&Y)<<C. - - - - --- 2022-08-08 Roger Sayle New
[Committed] Add -mno-stv to new gcc.target/i386/cmpti2.c test case. [Committed] Add -mno-stv to new gcc.target/i386/cmpti2.c test case. - - - - --- 2022-08-07 Roger Sayle New
middle-end: Optimize ((X >> C1) & C2) != C3 for more cases. middle-end: Optimize ((X >> C1) & C2) != C3 for more cases. - - - - --- 2022-08-07 Roger Sayle New
[x86,take,#2] Add peephole2 to reduce double word register shuffling [x86,take,#2] Add peephole2 to reduce double word register shuffling - - - - --- 2022-08-07 Roger Sayle New
[x86] Move V1TI shift/rotate lowering from expand to pre-reload split. [x86] Move V1TI shift/rotate lowering from expand to pre-reload split. - - - - --- 2022-08-05 Roger Sayle New
[x86_64] Allow any immediate constant in *cmp<dwi>_doubleword splitter. [x86_64] Allow any immediate constant in *cmp<dwi>_doubleword splitter. - - - - --- 2022-08-05 Roger Sayle New
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