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Tamar Christina
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| 603 patches
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Hauke
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Andes
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Apply
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
middle-end: check that the lhs of a COND_EXPR is an SSA_NAME in cond_store recognition [PR116628]
middle-end: check that the lhs of a COND_EXPR is an SSA_NAME in cond_store recognition [PR116628]
- - - -
-
-
-
2024-09-06
Tamar Christina
New
[4/4] AArch64: Define VECTOR_STORE_FLAG_VALUE.
[1/4] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available
- - - -
-
-
-
2024-09-03
Tamar Christina
New
[3/4,rtl] : simplify boolean vector EQ and NE comparisons
[1/4] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available
- - - -
-
-
-
2024-09-03
Tamar Christina
New
[2/4] middle-end: lower COND_EXPR into gimple form in vect_recog_bool_pattern
[1/4] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available
- - - -
-
-
-
2024-09-03
Tamar Christina
New
[1/4] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available
[1/4] middle-end: have vect_recog_cond_store_pattern use pattern statement for cond if available
- - - -
-
-
-
2024-09-03
Tamar Christina
New
[docs] : [committed] remove double mention of armv9-a.
[docs] : [committed] remove double mention of armv9-a.
- - - -
-
-
-
2024-09-03
Tamar Christina
New
[testsuite] : remove -fwrapv from signbit-5.c
[testsuite] : remove -fwrapv from signbit-5.c
- - - -
-
-
-
2024-09-03
Tamar Christina
New
[2/2] middle-end: use two's complement equality when comparing IVs during candidate selection [PR11…
[1/2] middle-end: refactor type to be explicit in operand_equal_p [PR114932]
- - - -
-
-
-
2024-08-20
Tamar Christina
New
[1/2] middle-end: refactor type to be explicit in operand_equal_p [PR114932]
[1/2] middle-end: refactor type to be explicit in operand_equal_p [PR114932]
- - - -
-
-
-
2024-08-20
Tamar Christina
New
AArch64: Fix signbit mask creation after late combine [PR116229]
AArch64: Fix signbit mask creation after late combine [PR116229]
- - - -
-
-
-
2024-08-07
Tamar Christina
New
middle-end: check for vector mode before in get_mask_mode [PR116074]
middle-end: check for vector mode before in get_mask_mode [PR116074]
- - - -
-
-
-
2024-07-26
Tamar Christina
New
[8/8] AArch64: take gather/scatter decode overhead into account
[1/8] AArch64: Update Neoverse V2 cost model to release costs
- - - -
-
-
-
2024-07-26
Tamar Christina
New
[7/8] AArch64: Add Cortex-X925 core definition and cost model
[1/8] AArch64: Update Neoverse V2 cost model to release costs
- - - -
-
-
-
2024-07-26
Tamar Christina
New
[6/8] AArch64: Update Neoverse N2 cost model to release costs
[1/8] AArch64: Update Neoverse V2 cost model to release costs
- - - -
-
-
-
2024-07-26
Tamar Christina
New
[5/8] AArch64: Update Generic Armv9-a cost model to release costs
[1/8] AArch64: Update Neoverse V2 cost model to release costs
- - - -
-
-
-
2024-07-26
Tamar Christina
New
[4/8] AArch64: Add Neoverse N3 and Cortex-A725 core definition and cost model
[1/8] AArch64: Update Neoverse V2 cost model to release costs
- - - -
-
-
-
2024-07-26
Tamar Christina
New
[3/8] AArch64: Add Neoverse V3AE core definition and cost model
[1/8] AArch64: Update Neoverse V2 cost model to release costs
- - - -
-
-
-
2024-07-26
Tamar Christina
New
[2/8] AArch64: Add Neoverse V3 core definition and cost model
[1/8] AArch64: Update Neoverse V2 cost model to release costs
- - - -
-
-
-
2024-07-26
Tamar Christina
New
[1/8] AArch64: Update Neoverse V2 cost model to release costs
[1/8] AArch64: Update Neoverse V2 cost model to release costs
- - - -
-
-
-
2024-07-26
Tamar Christina
New
AArch64: check for vector mode in get_mask_mode [PR116074]
AArch64: check for vector mode in get_mask_mode [PR116074]
- - - -
-
-
-
2024-07-26
Tamar Christina
New
[contrib] : support json output from check_GNU_style_lib.py
[contrib] : support json output from check_GNU_style_lib.py
- - - -
-
-
-
2024-07-18
Tamar Christina
New
middle-end: fix 0 offset creation and folding [PR115936]
middle-end: fix 0 offset creation and folding [PR115936]
- - - -
-
-
-
2024-07-16
Tamar Christina
New
[2/2] AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE [PR115531].
Untitled series #414603
- - - -
-
-
-
2024-07-10
Tamar Christina
New
[2/2] AArch64: lower 2 reg TBL permutes with one zero register to 1 reg TBL.
[1/2] AArch64: make aarch64_simd_vec_unpack<su>_lo_/_hi_ consistent.
- - - -
-
-
-
2024-07-04
Tamar Christina
New
[1/2] AArch64: make aarch64_simd_vec_unpack<su>_lo_/_hi_ consistent.
[1/2] AArch64: make aarch64_simd_vec_unpack<su>_lo_/_hi_ consistent.
- - - -
-
-
-
2024-07-04
Tamar Christina
New
[committed,testsuite] : Update test for PR115537 to use SVE .
[committed,testsuite] : Update test for PR115537 to use SVE .
- - - -
-
-
-
2024-07-04
Tamar Christina
New
[2/2] middle-end: replace constant_multiple_of with aff_combination_constant_multiple_p [PR114932]
[1/2] middle-end: fix wide_int_constant_multiple_p when VAL and DIV are 0. [PR114932]
- - - -
-
-
-
2024-07-01
Tamar Christina
New
[1/2] middle-end: fix wide_int_constant_multiple_p when VAL and DIV are 0. [PR114932]
[1/2] middle-end: fix wide_int_constant_multiple_p when VAL and DIV are 0. [PR114932]
- - - -
-
-
-
2024-07-01
Tamar Christina
New
middle-end: Implement conditonal store vectorizer pattern [PR115531]
middle-end: Implement conditonal store vectorizer pattern [PR115531]
- - - -
-
-
-
2024-06-25
Tamar Christina
New
[c++,frontend] : check for missing condition for novector [PR115623]
[c++,frontend] : check for missing condition for novector [PR115623]
- - - -
-
-
-
2024-06-25
Tamar Christina
New
[ivopts] : use affine_tree when comparing IVs during candidate selection [PR114932]
[ivopts] : use affine_tree when comparing IVs during candidate selection [PR114932]
- - - -
-
-
-
2024-06-14
Tamar Christina
New
[ivopts] : perform affine fold on unsigned addressing modes known not to overflow. [PR114932]
[ivopts] : perform affine fold on unsigned addressing modes known not to overflow. [PR114932]
- - - -
-
-
-
2024-06-14
Tamar Christina
New
AArch64: correct constraint on Upl early clobber alternatives
AArch64: correct constraint on Upl early clobber alternatives
- - - -
-
-
-
2024-06-06
Tamar Christina
New
[4/4] AArch64: enable new predicate tuning for Neoverse cores.
Untitled series #407712
- - - -
-
-
-
2024-05-22
Tamar Christina
New
[3/4] AArch64: add new alternative with early clobber to patterns
Untitled series #407712
- - - -
-
-
-
2024-05-22
Tamar Christina
New
[4/4] AArch64: enable new predicate tuning for Neoverse cores.
AArch64: support conditional early clobbers on certain operations.
- - - -
-
-
-
2024-05-15
Tamar Christina
New
[3/4] AArch64: add new alternative with early clobber to patterns
AArch64: support conditional early clobbers on certain operations.
- - - -
-
-
-
2024-05-15
Tamar Christina
New
[2/4] AArch64: add new tuning param and attribute for enabling conditional early clobber
AArch64: support conditional early clobbers on certain operations.
- - - -
-
-
-
2024-05-15
Tamar Christina
New
[1/4] AArch64: convert several predicate patterns to new compact syntax
AArch64: support conditional early clobbers on certain operations.
- - - -
-
-
-
2024-05-15
Tamar Christina
New
middle-end: refactory vect_recog_absolute_difference to simplify flow [PR114769]
middle-end: refactory vect_recog_absolute_difference to simplify flow [PR114769]
- - - -
-
-
-
2024-04-19
Tamar Christina
New
AArch64: remove reliance on register allocator for simd/gpreg costing. [PR114741]
AArch64: remove reliance on register allocator for simd/gpreg costing. [PR114741]
- - - -
-
-
-
2024-04-18
Tamar Christina
New
middle-end: skip vectorization check on ilp32 on vect-early-break_124-pr114403.c
middle-end: skip vectorization check on ilp32 on vect-early-break_124-pr114403.c
- - - -
-
-
-
2024-04-16
Tamar Christina
New
docs: document early break support and pragma novector
docs: document early break support and pragma novector
- - - -
-
-
-
2024-04-16
Tamar Christina
New
middle-end: adjust loop upper bounds when peeling for gaps and early break [PR114403].
middle-end: adjust loop upper bounds when peeling for gaps and early break [PR114403].
- - - -
-
-
-
2024-04-12
Tamar Christina
New
middle-end vect: adjust loop upper bounds when peeling for gaps and early break [PR114403]
middle-end vect: adjust loop upper bounds when peeling for gaps and early break [PR114403]
- - - -
-
-
-
2024-04-04
Tamar Christina
New
Summary: [PATCH][committed]AArch64: Do not allow SIMD clones with simdlen 1 [PR113552][GCC 13/12/11…
Summary: [PATCH][committed]AArch64: Do not allow SIMD clones with simdlen 1 [PR113552][GCC 13/12/11…
- - - -
-
-
-
2024-03-12
Tamar Christina
New
middle-end: delay updating of dominators until later during vectorization. [PR114081]
middle-end: delay updating of dominators until later during vectorization. [PR114081]
- - - -
-
-
-
2024-02-25
Tamar Christina
New
middle-end: update vuses out of loop which use a vdef that's moved [PR114068]
middle-end: update vuses out of loop which use a vdef that's moved [PR114068]
- - - -
-
-
-
2024-02-23
Tamar Christina
New
AArch64: xfail modes_1.f90 [PR107071]
AArch64: xfail modes_1.f90 [PR107071]
- - - -
-
-
-
2024-02-15
Tamar Christina
New
AArch64: remove ls64 from being mandatory on armv8.7-a..
AArch64: remove ls64 from being mandatory on armv8.7-a..
- - - -
-
-
-
2024-02-14
Tamar Christina
New
middle-end: inspect all exits for additional annotations for loop.
middle-end: inspect all exits for additional annotations for loop.
- - - -
-
-
-
2024-02-14
Tamar Christina
New
middle-end: update vector loop upper bounds when early break vect [PR113734]
middle-end: update vector loop upper bounds when early break vect [PR113734]
- - - -
-
-
-
2024-02-13
Tamar Christina
New
middle-end: add two debug counters for early-break vectorization debugging
middle-end: add two debug counters for early-break vectorization debugging
- - - -
-
-
-
2024-02-08
Tamar Christina
New
middle-end: don't cache restart_loop in vectorizable_live_operations [PR113808]
middle-end: don't cache restart_loop in vectorizable_live_operations [PR113808]
- - - -
-
-
-
2024-02-08
Tamar Christina
New
[committed] middle-end: fix pointer conversion error in testcase vect-early-break_110-pr113467.c
[committed] middle-end: fix pointer conversion error in testcase vect-early-break_110-pr113467.c
- - - -
-
-
-
2024-02-08
Tamar Christina
New
middle-end: fix ICE when destination BB for stores starts with a label [PR113750]
middle-end: fix ICE when destination BB for stores starts with a label [PR113750]
- - - -
-
-
-
2024-02-05
Tamar Christina
New
middle-end: fix ICE when moving statements to empty BB [PR113731]
middle-end: fix ICE when moving statements to empty BB [PR113731]
- - - -
-
-
-
2024-02-05
Tamar Christina
New
middle-end: add additional runtime test for [PR113467]
middle-end: add additional runtime test for [PR113467]
- - - -
-
-
-
2024-02-05
Tamar Christina
New
AArch64: update vget_set_lane_1.c test output
AArch64: update vget_set_lane_1.c test output
- - - -
-
-
-
2024-02-01
Tamar Christina
New
[2/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644]
[1/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644]
- - - -
-
-
-
2024-01-31
Tamar Christina
New
[1/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644]
[1/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644]
- - - -
-
-
-
2024-01-31
Tamar Christina
New
middle-end: check memory accesses in the destination block [PR113588].
middle-end: check memory accesses in the destination block [PR113588].
- - - -
-
-
-
2024-01-29
Tamar Christina
New
AArch64: relax cbranch tests to accepted inverted branches [PR113502]
AArch64: relax cbranch tests to accepted inverted branches [PR113502]
- - - -
-
-
-
2024-01-29
Tamar Christina
New
[libsanitizer] : Sync fixes for asan interceptors from upstream [PR112644]
[libsanitizer] : Sync fixes for asan interceptors from upstream [PR112644]
- - - -
-
-
-
2024-01-29
Tamar Christina
New
AArch64: Fix expansion of Advanced SIMD div and mul using SVE [PR109636]
AArch64: Fix expansion of Advanced SIMD div and mul using SVE [PR109636]
- - - -
-
-
-
2024-01-24
Tamar Christina
New
AArch64: Do not allow SIMD clones with simdlen 1 [PR113552]
AArch64: Do not allow SIMD clones with simdlen 1 [PR113552]
- - - -
-
-
-
2024-01-24
Tamar Christina
New
middle-end: rename main_exit_p in reduction code.
middle-end: rename main_exit_p in reduction code.
- - - -
-
-
-
2024-01-23
Tamar Christina
New
middle-end: fix epilog reductions when vector iters peeled [PR113364]
middle-end: fix epilog reductions when vector iters peeled [PR113364]
- - - -
-
-
-
2024-01-23
Tamar Christina
New
middle-end: remove more usages of single_exit
middle-end: remove more usages of single_exit
- - - -
-
-
-
2024-01-12
Tamar Christina
New
middle-end testsuite: remove -save-temps from many tests [PR113319]
middle-end testsuite: remove -save-temps from many tests [PR113319]
- - - -
-
-
-
2024-01-11
Tamar Christina
New
middle-end: make memory analysis for early break more deterministic [PR113135]
middle-end: make memory analysis for early break more deterministic [PR113135]
- - - -
-
-
-
2024-01-11
Tamar Christina
New
middle-end: fill in reduction PHI for all alt exits [PR113144]
middle-end: fill in reduction PHI for all alt exits [PR113144]
- - - -
-
-
-
2024-01-11
Tamar Christina
New
[testsuite] : Make bitint early vect test more accurate
[testsuite] : Make bitint early vect test more accurate
- - - -
-
-
-
2024-01-10
Tamar Christina
New
middle-end: correctly identify the edge taken when condition is true. [PR113287]
middle-end: correctly identify the edge taken when condition is true. [PR113287]
- - - -
-
-
-
2024-01-10
Tamar Christina
New
[committed,c++,frontend] : initialize ivdep value
[committed,c++,frontend] : initialize ivdep value
- - - -
-
-
-
2024-01-10
Tamar Christina
New
[committed] middle-end: removed unused variable in vectorizable_live_operation_1
[committed] middle-end: removed unused variable in vectorizable_live_operation_1
- - - -
-
-
-
2024-01-09
Tamar Christina
New
Arm: Update early-break tests to accept thumb output too.
Arm: Update early-break tests to accept thumb output too.
- - - -
-
-
-
2024-01-09
Tamar Christina
New
[frontend] : don't ice with pragma NOVECTOR if loop in C has no condition [PR113267]
[frontend] : don't ice with pragma NOVECTOR if loop in C has no condition [PR113267]
- - - -
-
-
-
2024-01-08
Tamar Christina
New
middle-end: thread through existing LCSSA variable for alternative exits too [PR113237]
middle-end: thread through existing LCSSA variable for alternative exits too [PR113237]
- - - -
-
-
-
2024-01-07
Tamar Christina
New
middle-end: Don't apply copysign optimization if target does not implement optab [PR112468]
middle-end: Don't apply copysign optimization if target does not implement optab [PR112468]
- - - -
-
-
-
2024-01-04
Tamar Christina
New
middle-end: check if target can do extract first for early breaks [PR113199]
middle-end: check if target can do extract first for early breaks [PR113199]
- - - -
-
-
-
2024-01-02
Tamar Christina
New
middle-end: maintain LCSSA form when peeled vector iterations have virtual operands
middle-end: maintain LCSSA form when peeled vector iterations have virtual operands
- - - -
-
-
-
2023-12-29
Tamar Christina
New
middle-end: Fix dominators updates when peeling with multiple exits [PR113144]
middle-end: Fix dominators updates when peeling with multiple exits [PR113144]
- - - -
-
-
-
2023-12-29
Tamar Christina
New
middle-end: rejects loops with nonlinear inductions and early breaks [PR113163]
middle-end: rejects loops with nonlinear inductions and early breaks [PR113163]
- - - -
-
-
-
2023-12-29
Tamar Christina
New
[20/21] Arm: Add Advanced SIMD cbranch implementation
Untitled series #388362
- - - -
-
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2023-12-29
Tamar Christina
New
AArch64 Update costing for vector conversions [PR110625]
AArch64 Update costing for vector conversions [PR110625]
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2023-12-29
Tamar Christina
New
[committed] middle-end: explicitly initialize vec_stmts [PR113132]
[committed] middle-end: explicitly initialize vec_stmts [PR113132]
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2023-12-25
Tamar Christina
New
[testsuite] : Add more pragma novector to new tests
[testsuite] : Add more pragma novector to new tests
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2023-12-24
Tamar Christina
New
[2/21] middle-end testsuite: Add tests for early break vectorization
Untitled series #387734
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2023-12-21
Tamar Christina
New
middle-end: Handle hybrid SLP induction vectorization with early breaks.
middle-end: Handle hybrid SLP induction vectorization with early breaks.
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2023-12-19
Tamar Christina
New
middle-end: Mark all control flow as used_in_scope.
middle-end: Mark all control flow as used_in_scope.
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2023-12-11
Tamar Christina
New
middle-end: Fix peeled vect loop IV values.
middle-end: Fix peeled vect loop IV values.
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2023-12-06
Tamar Christina
New
middle-end: correct loop bounds for early breaks and peeled vector loops
middle-end: correct loop bounds for early breaks and peeled vector loops
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2023-12-06
Tamar Christina
New
middle-end: refactor vectorizable_live_operation into helper method for codegen
middle-end: refactor vectorizable_live_operation into helper method for codegen
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2023-11-27
Tamar Christina
New
middle-end: prevent LIM from hoising vector compares from gconds if target does not support it.
middle-end: prevent LIM from hoising vector compares from gconds if target does not support it.
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2023-11-27
Tamar Christina
New
AArch64: fix aarch64_usubw pattern
AArch64: fix aarch64_usubw pattern
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2023-11-22
Tamar Christina
New
AArch64 docs: update -mcpu=generic definition on aarch64
AArch64 docs: update -mcpu=generic definition on aarch64
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2023-11-16
Tamar Christina
New
[6/6] AArch64: only emit mismatch error when features would be disabled.
[1/6] AArch64: Refactor costs models to different files.
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2023-11-15
Tamar Christina
New
[4/6] AArch64: Add new generic-armv9-a CPU and make it the default for Armv9
[1/6] AArch64: Refactor costs models to different files.
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2023-11-15
Tamar Christina
New
[3/6] AArch64: Add new generic-armv8-a CPU and make it the default.
[1/6] AArch64: Refactor costs models to different files.
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2023-11-15
Tamar Christina
New
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