From patchwork Fri Sep 22 07:11:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1837981 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=irq.a4lg.com header.i=@irq.a4lg.com header.a=rsa-sha256 header.s=2017s01 header.b=krzGxi0j; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RsNk40Dglz1yh6 for ; Fri, 22 Sep 2023 17:11:54 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1583D3857732 for ; Fri, 22 Sep 2023 07:11:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id C7DC93858D33 for ; Fri, 22 Sep 2023 07:11:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C7DC93858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id B1CBC300089; Fri, 22 Sep 2023 07:11:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1695366692; bh=naLneTReNpPR/tYZU5WCkbuOfE2dAZQsQKiJwYlw2W4=; h=From:To:Cc:Subject:Date:Message-ID:Mime-Version: Content-Transfer-Encoding; b=krzGxi0juWfwNP/bFxcdygG+5E4regGPMEFx2N53SCZj0PsBs9CC1CvL7lU3eo6+5 6V+T2fQE5btZg3g1xbBKOS/DdBx3dRBlarLu/VE/wISsofiKC+JMKibhLLyPz4IMUk LAn9NUWLee4/WNu07KUbc7cvGjNSwxtenrbsbfUA= From: Tsukasa OI To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 0/2] RISC-V: Define not broken prefetch builtins Date: Fri, 22 Sep 2023 07:11:15 +0000 Message-ID: Mime-Version: 1.0 X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, KAM_MANYTO, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hello, As I explained earlier: , the builtin function for RISC-V "__builtin_riscv_zicbop_cbo_prefetchi" is completely broken. Instead, this patch set (in PATCH 1/2) creates three new, working builtin intrinsics. void __builtin_riscv_prefetch_i(void *addr, [intptr_t offset,] ...); void __builtin_riscv_prefetch_r(void *addr, [intptr_t offset,] ...); void __builtin_riscv_prefetch_w(void *addr, [intptr_t offset,] ...); For consistency with "prefetch.i" and the reason I describe later (which requires native instructions for "prefetch.r" and "prefetch.w"), I decided to make builtin functions for "prefetch.[rw]" as well. Optional second argument (named "offset" here) defaults to zero and must be a compile-time integral constant. Also, it must be a valid offset for a "prefetch.[irw]" HINT instruction (x % 32 == 0 && x >= -2048 && x < 2048). They are defined if the 'Zicbop' extension is supported and expands to: > prefetch.i offset(addr_reg) ; __builtin_riscv_prefetch_i > prefetch.r offset(addr_reg) ; __builtin_riscv_prefetch_r > prefetch.w offset(addr_reg) ; __builtin_riscv_prefetch_w The hardest part of this patch set was to support builtin function with variable argument (making "offset" optional). It required: 1. Support for variable argument function prototype for RISC-V builtins (corresponding "..." on C-based languages) 2. Support for (non-vector) RISC-V builtins with custom expansion (on RVV intrinsics, custom expansion is already implemented) ... and PATCH 2/2 fixes an ICE while I'm investigating regular prefetch builtin (__builtin_prefetch). If the 'Zicbop' extension is enabled, __builtin_prefetch with the first argument NULL or (not all but) some fixed addresses (like ((void*)0x20)) can cause an ICE. This is because the "r" constraint is not checked and a constant can be a first argument of target-specific "prefetch" RTL instruction. PATCH 2/2 fixes this issue by: 1. Making "prefetch" not an instruction but instead an expansion (this is not rare; e.g. on i386) and 2. Coercing the address argument into a register in the expansion It requires separate instructions for "prefetch.[rw]" and I decided to make those prefetch instructions very similar to "prefetch.i". That's one of the reasons I created builtins corresponding those. Sincerely, Tsukasa Tsukasa OI (2): RISC-V: Define not broken prefetch builtins RISC-V: Fix ICE by expansion and register coercion gcc/config/riscv/riscv-builtins.cc | 112 +++++++++++++++++- gcc/config/riscv/riscv-cmo.def | 8 +- gcc/config/riscv/riscv-ftypes.def | 1 + gcc/config/riscv/riscv.md | 67 ++++++++--- gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 41 ++++--- gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 33 ++---- gcc/testsuite/gcc.target/riscv/cmo-zicbop-3.c | 29 +++++ gcc/testsuite/gcc.target/riscv/cmo-zicbop-4.c | 14 +++ gcc/testsuite/gcc.target/riscv/cmo-zicbop-5.c | 14 +++ gcc/testsuite/gcc.target/riscv/cmo-zicbop-6.c | 38 ++++++ .../gcc.target/riscv/cmo-zicbop-by-common-1.c | 17 +++ .../gcc.target/riscv/cmo-zicbop-by-common-2.c | 7 ++ .../gcc.target/riscv/cmo-zicbop-by-common-3.c | 13 ++ .../riscv/cmo-zicbop-by-common-ice-1.c | 13 ++ .../riscv/cmo-zicbop-by-common-ice-2.c | 7 ++ 15 files changed, 350 insertions(+), 64 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c base-commit: 40ac613627205dd4d24ae136917e48b357fee758