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[0/3] RISC-V: Add stub support for existing extensions

Message ID cover.1691809036.git.research_trasio@irq.a4lg.com
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Series RISC-V: Add stub support for existing extensions | expand

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Tsukasa OI Aug. 12, 2023, 2:57 a.m. UTC 
Hello,

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects, GCC should
support almost all extensions that Binutils support, even if the GCC does
not touch a thing.

In this patch set, it adds stub extension support along with its
implications (for GCC preprocessor support).

The author excluded those extensions:

1.  'Zicntr' and 'Zihpm'
    (because additional compatibility measures are required)
2.  'Q' and "Zqinx"
    (because GCC does not support 'Q' and 'Zqinx' is not ratified)

and included following extensions not yet supported by Binutils:

*   'Zcmp', 'Zcmt' and 'Zce' extensions
    They are ratified and if we only need a stub support, it's relatively
    easy to implement.

This patch set consists of three patches:

1.  Privileged Extensions
    Unlikely to cause merge conflicts and easy to implement.
2.  Vendor Extension ('XVentanaCondOps')
    Unlikely to cause merge conflicts unless someone tries to merge
    optimization using 'Zicond' with 'XVentanaCondOps' (because 'Zicond' and
    'XVentanaCondOps' are pretty much the same except encodings).
3.  Standard Unprivileged Extensions
    Likely to cause merge conflicts depending on the order to apply patches.
    In that case, prefer others (because this patchset adds *stub* support
    for those extensions).

On this patch set, I focused on adding stub support for new extensions in
GCC (in the GCC perspective) and not all Binutils' contents are ported.

I'll submit separate patch set to port additional implications (e.g.
'M' -> 'Zmmul', 'Zve32x' -> 'Zicsr').

And despite that I implemented stub 'Zce' support, its implications are not
complete (e.g. 'Zce' + 'F' -> 'Zcf' is not implemented and planned for the
next patch set).

Thanks,
Tsukasa




Tsukasa OI (3):
  RISC-V: Add stub support for existing extensions (privileged)
  RISC-V: Add stub support for existing extensions (vendor)
  RISC-V: Add stub support for existing extensions (unprivileged)

 gcc/common/config/riscv/riscv-common.cc    | 45 ++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/predef-29.c | 35 +++++++++++++++++
 gcc/testsuite/gcc.target/riscv/predef-30.c | 27 +++++++++++++
 gcc/testsuite/gcc.target/riscv/predef-31.c | 31 +++++++++++++++
 4 files changed, 138 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-29.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-30.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c


base-commit: 8be20733b38c200f375cacf698d6b85e76055bcd