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[V2,0/2] RISC-V:Add Cache Management Operation ISA Extensions Intrinsics

Message ID 20241029101234.985973-1-shiyulong@iscas.ac.cn
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Series RISC-V:Add Cache Management Operation ISA Extensions Intrinsics | expand

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yulong Oct. 29, 2024, 10:12 a.m. UTC 
From: yulong <shiyulong@iscas.ac.cn>

This patchset adds intrinsic support for CMOs extensions.

cf. <https://github.com/riscv-non-isa/riscv-c-api-doc/pull/93>;

Patch 1: Add Zicbom/z/p intrinsic support
Patch 2: Add test cases.

Diff with V1: Add intrinsic support for the prefetchi instruction.

yulong (2):
  RISC-V:Add intrinsic support for the CMOs extensions
  RISC-V:Add intrinsic cases for the CMOs extensions

 gcc/config.gcc                          |  2 +-
 gcc/config/riscv/riscv_cmo.h            | 93 +++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/cmo-32.c | 58 +++++++++++++++
 gcc/testsuite/gcc.target/riscv/cmo-64.c | 58 +++++++++++++++
 4 files changed, 210 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv_cmo.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-64.c