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[80.3.10.149]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43160dc9a89sm23577435e9.16.2024.10.18.06.13.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2024 06:13:57 -0700 (PDT) From: Craig Blackmore To: gcc-patches@gcc.gnu.org Cc: Craig Blackmore Subject: [PATCH 0/7] RISC-V: Vector memcpy/memset fixes and improvements Date: Fri, 18 Oct 2024 14:12:53 +0100 Message-ID: <20241018131300.1150819-1-craig.blackmore@embecosm.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The main aim of this patch series is to make inline vector memcpy respect -mrvv-max-lmul and to extend inline vector memset to be used in more cases. It includes some preparatory fixes and refactoring along the way. Craig Blackmore (7): RISC-V: Fix indentation in riscv_vector::expand_block_move [NFC] RISC-V: Fix uninitialized reg in memcpy RISC-V: Fix vector memcpy smaller LMUL generation RISC-V: Honour -mrvv-max-lmul in riscv_vector::expand_block_move RISC-V: Move vector memcpy decision making to separate function [NFC] RISC-V: Make vectorized memset handle more cases RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD gcc/config/riscv/riscv-protos.h | 3 +- gcc/config/riscv/riscv-string.cc | 292 +++++++++++------- gcc/config/riscv/riscv-v.cc | 12 + gcc/config/riscv/riscv.cc | 19 ++ gcc/config/riscv/riscv.md | 12 +- .../gcc.target/riscv/rvv/autovec/pr113206-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr113206-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr113469.c | 3 +- .../rvv/autovec/vls/calling-convention-1.c | 11 +- .../rvv/autovec/vls/calling-convention-2.c | 11 +- .../rvv/autovec/vls/calling-convention-3.c | 11 +- .../rvv/autovec/vls/calling-convention-4.c | 8 +- .../rvv/autovec/vls/calling-convention-5.c | 11 +- .../rvv/autovec/vls/calling-convention-6.c | 11 +- .../rvv/autovec/vls/calling-convention-7.c | 8 +- .../riscv/rvv/autovec/vls/spill-4.c | 2 +- .../riscv/rvv/autovec/vls/spill-7.c | 2 +- .../gcc.target/riscv/rvv/base/cpymem-1.c | 4 +- .../gcc.target/riscv/rvv/base/cpymem-2.c | 2 +- .../gcc.target/riscv/rvv/base/cpymem-3.c | 85 +++++ .../gcc.target/riscv/rvv/base/movmem-1.c | 7 +- .../gcc.target/riscv/rvv/base/pr111720-0.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-1.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-2.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-3.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-4.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-5.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-6.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-7.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-8.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-9.c | 2 +- .../gcc.target/riscv/rvv/base/setmem-1.c | 37 ++- .../gcc.target/riscv/rvv/base/setmem-2.c | 49 ++- .../gcc.target/riscv/rvv/base/setmem-3.c | 53 +++- .../gcc.target/riscv/rvv/vsetvl/pr112929-1.c | 6 +- .../gcc.target/riscv/rvv/vsetvl/pr112988-1.c | 6 +- 36 files changed, 463 insertions(+), 226 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c