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X-CSE-ConnectionGUID: 8+PUFvogSBa+LFYhbdkQ9Q== X-CSE-MsgGUID: uKWQz/6ZSgOr8HxfG7FS8w== X-IronPort-AV: E=McAfee;i="6700,10204,11225"; a="28465085" X-IronPort-AV: E=Sophos;i="6.11,204,1725346800"; d="scan'208";a="28465085" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2024 20:29:57 -0700 X-CSE-ConnectionGUID: WB2AXDk7QqCru2/40pt9mw== X-CSE-MsgGUID: NQeWB+h6Ss2t9Zqdp4pJBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,204,1725346800"; d="scan'208";a="82381259" Received: from shliclel4217.sh.intel.com ([10.239.240.127]) by fmviesa004.fm.intel.com with ESMTP; 14 Oct 2024 20:29:56 -0700 From: liuhongt To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, jeffreyalaw@gmail.com Subject: [PATCH 0/2] Canonicalize (vec_merge (fma op1 op2 op3) op1 mask) to (vec_merge (fma op1 op2 op3) op1 mask) Date: Tue, 15 Oct 2024 11:29:53 +0800 Message-Id: <20241015032955.3677006-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <7p8r18n6-668q-37pr-7o70-74rr02673919@fhfr.qr> References: <7p8r18n6-668q-37pr-7o70-74rr02673919@fhfr.qr> MIME-Version: 1.0 X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org For x86 masked fma, there're 2 rtl representations 1) (vec_merge (fma op2 op1 op3) op1 mask) 2) (vec_merge (fma op1 op2 op3) op1 mask). 5894(define_insn "_fmadd__mask" 5895 [(set (match_operand:VFH_AVX512VL 0 "register_operand" "=v,v") 5896 (vec_merge:VFH_AVX512VL 5897 (fma:VFH_AVX512VL 5898 (match_operand:VFH_AVX512VL 1 "nonimmediate_operand" "0,0") 5899 (match_operand:VFH_AVX512VL 2 "" ",v") 5900 (match_operand:VFH_AVX512VL 3 "" "v,")) 5901 (match_dup 1) 5902 (match_operand: 4 "register_operand" "Yk,Yk")))] 5903 "TARGET_AVX512F && " 5904 "@ 5905 vfmadd132\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2} 5906 vfmadd213\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}" 5907 [(set_attr "type" "ssemuladd") 5908 (set_attr "prefix" "evex") 5909 (set_attr "mode" "")]) Here op1 has constraint "0", and the scecond op1 is (match_dup 1), we once tried to replace it with (match_operand:M 5 "nonimmediate_operand" "0")) to enable more flexibility for pattern match and recog, but it triggered an ICE in reload(reload can handle at most one perand with "0" constraint). So we need either add 2 patterns in the backend or just do the canonicalization in the middle-end. The patch canonicalize it at combine, and adjust x86 backend patterns. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Any comments? liuhongt (2): Canonicalize (vec_merge (fma op2 op1 op3) op1 mask) to (vec_merge (fma op1 op2 op3) op1 mask). [x86] Canonicalize (vec_merge (fma: op2 op1 op3) (match_dup 1)) mask) to (vec_merge (fma: op1 op2 op3) (match_dup 1)) mask) gcc/combine.cc | 25 ++++++++++++ gcc/config/i386/sse.md | 86 +++++++++++++++++++++--------------------- 2 files changed, 68 insertions(+), 43 deletions(-)