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[v3,00/12] arm: vld1q vst1 vst1q vst1 intrinsics

Message ID 20240102092345.28370-1-Ezra.Sitorus@arm.com
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Series arm: vld1q vst1 vst1q vst1 intrinsics | expand

Message

Ezra Sitorus Jan. 2, 2024, 9:23 a.m. UTC 
From: Ezra Sitorus <ezra.sitorus@arm.com>

Add vld1q, vst1, vst1q and vst1 intrinsics to arm port.

Ezra Sitorus (12):
  [GCC] arm: vld1q_types_x2 ACLE intrinsics
  [GCC] arm: vld1q_types_x3 ACLE intrinsics
  [GCC] arm: vld1q_types_x4 ACLE intrinsics
  [GCC] arm: vst1_types_x2 ACLE intrinsics
  [GCC] arm: vst1_types_x3 ACLE intrinsics
  [GCC] arm: vst1_types_x4 ACLE intrinsics
  [GCC] arm: vst1q_types_x2 ACLE intrinsics
  [GCC] arm: vst1q_types_x3 ACLE intrinsics
  [GCC] arm: vst1q_types_x4 ACLE intrinsics
  [GCC] arm: vld1_types_x2 ACLE intrinsics
  [GCC] arm: vld1_types_x3 ACLE intrinsics
  [GCC] arm: vld1_types_x4 ACLE intrinsics

 gcc/config/arm/arm_neon.h                     | 2032 ++++++++++++++---
 gcc/config/arm/arm_neon_builtins.def          |   12 +
 gcc/config/arm/iterators.md                   |    6 +
 gcc/config/arm/neon.md                        |  249 ++
 gcc/config/arm/unspecs.md                     |    8 +
 .../gcc.target/arm/simd/vld1_base_xN_1.c      |  176 ++
 .../gcc.target/arm/simd/vld1_bf16_xN_1.c      |   23 +
 .../gcc.target/arm/simd/vld1_fp16_xN_1.c      |   23 +
 .../gcc.target/arm/simd/vld1_p64_xN_1.c       |   23 +
 .../gcc.target/arm/simd/vld1q_base_xN_1.c     |  183 ++
 .../gcc.target/arm/simd/vld1q_bf16_xN_1.c     |   24 +
 .../gcc.target/arm/simd/vld1q_fp16_xN_1.c     |   24 +
 .../gcc.target/arm/simd/vld1q_p64_xN_1.c      |   24 +
 .../gcc.target/arm/simd/vst1_base_xN_1.c      |  176 ++
 .../gcc.target/arm/simd/vst1_bf16_xN_1.c      |   22 +
 .../gcc.target/arm/simd/vst1_fp16_xN_1.c      |   23 +
 .../gcc.target/arm/simd/vst1_p64_xN_1.c       |   23 +
 .../gcc.target/arm/simd/vst1q_base_xN_1.c     |  185 ++
 .../gcc.target/arm/simd/vst1q_bf16_xN_1.c     |   24 +
 .../gcc.target/arm/simd/vst1q_fp16_xN_1.c     |   24 +
 .../gcc.target/arm/simd/vst1q_p64_xN_1.c      |   24 +
 21 files changed, 3018 insertions(+), 290 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c

Comments

Richard Earnshaw (lists) Jan. 12, 2024, 5:03 p.m. UTC | #1 
On 02/01/2024 09:23, Ezra.Sitorus@arm.com wrote:
> From: Ezra Sitorus <ezra.sitorus@arm.com>
> 
> Add vld1q, vst1, vst1q and vst1 intrinsics to arm port.
> 
> Ezra Sitorus (12):
>   [GCC] arm: vld1q_types_x2 ACLE intrinsics
>   [GCC] arm: vld1q_types_x3 ACLE intrinsics
>   [GCC] arm: vld1q_types_x4 ACLE intrinsics
>   [GCC] arm: vst1_types_x2 ACLE intrinsics
>   [GCC] arm: vst1_types_x3 ACLE intrinsics
>   [GCC] arm: vst1_types_x4 ACLE intrinsics
>   [GCC] arm: vst1q_types_x2 ACLE intrinsics
>   [GCC] arm: vst1q_types_x3 ACLE intrinsics
>   [GCC] arm: vst1q_types_x4 ACLE intrinsics
>   [GCC] arm: vld1_types_x2 ACLE intrinsics
>   [GCC] arm: vld1_types_x3 ACLE intrinsics
>   [GCC] arm: vld1_types_x4 ACLE intrinsics
> 
>  gcc/config/arm/arm_neon.h                     | 2032 ++++++++++++++---
>  gcc/config/arm/arm_neon_builtins.def          |   12 +
>  gcc/config/arm/iterators.md                   |    6 +
>  gcc/config/arm/neon.md                        |  249 ++
>  gcc/config/arm/unspecs.md                     |    8 +
>  .../gcc.target/arm/simd/vld1_base_xN_1.c      |  176 ++
>  .../gcc.target/arm/simd/vld1_bf16_xN_1.c      |   23 +
>  .../gcc.target/arm/simd/vld1_fp16_xN_1.c      |   23 +
>  .../gcc.target/arm/simd/vld1_p64_xN_1.c       |   23 +
>  .../gcc.target/arm/simd/vld1q_base_xN_1.c     |  183 ++
>  .../gcc.target/arm/simd/vld1q_bf16_xN_1.c     |   24 +
>  .../gcc.target/arm/simd/vld1q_fp16_xN_1.c     |   24 +
>  .../gcc.target/arm/simd/vld1q_p64_xN_1.c      |   24 +
>  .../gcc.target/arm/simd/vst1_base_xN_1.c      |  176 ++
>  .../gcc.target/arm/simd/vst1_bf16_xN_1.c      |   22 +
>  .../gcc.target/arm/simd/vst1_fp16_xN_1.c      |   23 +
>  .../gcc.target/arm/simd/vst1_p64_xN_1.c       |   23 +
>  .../gcc.target/arm/simd/vst1q_base_xN_1.c     |  185 ++
>  .../gcc.target/arm/simd/vst1q_bf16_xN_1.c     |   24 +
>  .../gcc.target/arm/simd/vst1q_fp16_xN_1.c     |   24 +
>  .../gcc.target/arm/simd/vst1q_p64_xN_1.c      |   24 +
>  21 files changed, 3018 insertions(+), 290 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
> 

Thanks, I've pushed this series.

Reviewing this series did highlight a couple of issues with the existing code base (not your patch); I'll follow up on these separately.

R.