From patchwork Fri Nov 17 08:19:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: joshua X-Patchwork-Id: 1864976 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4SWqbQ4TY3z1yS6 for ; Fri, 17 Nov 2023 19:20:34 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C944B3857B9B for ; Fri, 17 Nov 2023 08:20:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-124.freemail.mail.aliyun.com (out30-124.freemail.mail.aliyun.com [115.124.30.124]) by sourceware.org (Postfix) with ESMTPS id 1D4BB3858C41 for ; Fri, 17 Nov 2023 08:20:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1D4BB3858C41 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1D4BB3858C41 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700209219; cv=none; b=T3yo6UijXQT96voJ8Xfvy7nznuyuTVpN4LQE6CD9IduUwcBVJnCKAVzamPFNVFPXOoJytrfOkbCi0XKx1TpZKldUNR6iOLTp+M6VZV2CM0tIGUnCULDoK6jwo6n8gWXBki2e0CFvTKpGbDb9PIiKbbvzqVQ799Na5oaRbIGQgI8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700209219; c=relaxed/simple; bh=7EtiafSKpOYsknzkzRHxp0ZVO7I8eAb0dri+RDm1IdA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=iV6A9joIbsJqV/3x7Hytiso9yRmc0zyVXojWondHM3T+JCRHHkBpSaUMxZl3uzIwvHM7hCy90myvm+1vhSPLM0y80H2X3qj6mGXdpd4W43JBht35xx/cD8wcZt7zzI7JXrGMuuSFVipRdGKOaKsfcmv/TDuCh5l1UJJ8M01hxkQ= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R981e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046056; MF=cooper.joshua@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0VwYuxUE_1700209208; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0VwYuxUE_1700209208) by smtp.aliyun-inc.com; Fri, 17 Nov 2023 16:20:11 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, "Jun Sha (Joshua)" Subject: [PATCH 0/9] RISC-V: Support XTheadVector extensions Date: Fri, 17 Nov 2023 16:19:55 +0800 Message-Id: <20231117081955.2395-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 MIME-Version: 1.0 X-Spam-Status: No, score=-14.5 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ Contributors: Jun Sha (Joshua) Jin Ma RISC-V: minimal support for xtheadvector RISC-V: Handle differences between xtheadvector and vector RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1) RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2) RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3) RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4) RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part5) RISC-V: Add support for xtheadvector-specific load/store intrinsics RISC-V: Disable fractional type intrinsics for XTheadVector --- gcc/common/config/riscv/riscv-common.cc | 10 + gcc/config.gcc | 2 +- gcc/config/riscv/riscv-c.cc | 8 +- gcc/config/riscv/riscv-protos.h | 1 + .../riscv/riscv-vector-builtins-bases.cc | 122 +++ .../riscv/riscv-vector-builtins-bases.h | 30 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/riscv-vector-builtins-shapes.cc | 122 +++ .../riscv/riscv-vector-builtins-shapes.h | 2 + .../riscv/riscv-vector-builtins-types.def | 120 +++ gcc/config/riscv/riscv-vector-builtins.cc | 300 ++++++- gcc/config/riscv/riscv-vector-switch.def | 144 ++-- gcc/config/riscv/riscv.cc | 13 +- gcc/config/riscv/riscv.opt | 2 + gcc/config/riscv/riscv_th_vector.h | 49 ++ .../riscv/thead-vector-builtins-functions.def | 30 + gcc/config/riscv/thead-vector.md | 235 ++++++ gcc/config/riscv/vector-iterators.md | 4 + gcc/config/riscv/vector.md | 778 +++++++++--------- .../riscv/predef-__riscv_th_v_intrinsic.c | 11 + .../gcc.target/riscv/rvv/base/pragma-1.c | 2 +- .../gcc.target/riscv/rvv/fractional-type.c | 79 ++ .../gcc.target/riscv/rvv/xtheadvector.c | 13 + .../rvv/xtheadvector/autovec/vadd-run-nofm.c | 4 + .../riscv/rvv/xtheadvector/autovec/vadd-run.c | 81 ++ .../xtheadvector/autovec/vadd-rv32gcv-nofm.c | 10 + .../rvv/xtheadvector/autovec/vadd-rv32gcv.c | 8 + .../xtheadvector/autovec/vadd-rv64gcv-nofm.c | 10 + .../rvv/xtheadvector/autovec/vadd-rv64gcv.c | 8 + .../rvv/xtheadvector/autovec/vadd-template.h | 70 ++ .../rvv/xtheadvector/autovec/vadd-zvfh-run.c | 54 ++ .../riscv/rvv/xtheadvector/autovec/vand-run.c | 75 ++ .../rvv/xtheadvector/autovec/vand-rv32gcv.c | 7 + .../rvv/xtheadvector/autovec/vand-rv64gcv.c | 7 + .../rvv/xtheadvector/autovec/vand-template.h | 61 ++ .../rvv/xtheadvector/binop_vv_constraint-1.c | 68 ++ .../rvv/xtheadvector/binop_vv_constraint-3.c | 27 + .../rvv/xtheadvector/binop_vv_constraint-4.c | 27 + .../rvv/xtheadvector/binop_vv_constraint-5.c | 29 + .../rvv/xtheadvector/binop_vv_constraint-6.c | 28 + .../rvv/xtheadvector/binop_vv_constraint-7.c | 29 + .../rvv/xtheadvector/binop_vx_constraint-1.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-10.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-11.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-12.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-13.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-14.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-15.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-16.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-17.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-18.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-19.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-2.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-20.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-21.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-22.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-23.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-24.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-25.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-26.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-27.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-28.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-29.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-3.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-30.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-31.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-32.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-33.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-34.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-35.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-36.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-37.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-38.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-39.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-4.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-40.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-41.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-42.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-43.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-44.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-45.c | 123 +++ .../rvv/xtheadvector/binop_vx_constraint-46.c | 72 ++ .../rvv/xtheadvector/binop_vx_constraint-47.c | 16 + .../rvv/xtheadvector/binop_vx_constraint-48.c | 16 + .../rvv/xtheadvector/binop_vx_constraint-49.c | 16 + .../rvv/xtheadvector/binop_vx_constraint-5.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-50.c | 18 + .../rvv/xtheadvector/binop_vx_constraint-6.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-7.c | 68 ++ .../rvv/xtheadvector/binop_vx_constraint-8.c | 73 ++ .../rvv/xtheadvector/binop_vx_constraint-9.c | 68 ++ .../rvv/xtheadvector/rvv-xtheadvector.exp | 41 + .../rvv/xtheadvector/ternop_vv_constraint-1.c | 83 ++ .../rvv/xtheadvector/ternop_vv_constraint-2.c | 83 ++ .../rvv/xtheadvector/ternop_vv_constraint-3.c | 83 ++ .../rvv/xtheadvector/ternop_vv_constraint-4.c | 83 ++ .../rvv/xtheadvector/ternop_vv_constraint-5.c | 83 ++ .../rvv/xtheadvector/ternop_vv_constraint-6.c | 83 ++ .../rvv/xtheadvector/ternop_vx_constraint-1.c | 71 ++ .../rvv/xtheadvector/ternop_vx_constraint-2.c | 38 + .../rvv/xtheadvector/ternop_vx_constraint-3.c | 125 +++ .../rvv/xtheadvector/ternop_vx_constraint-4.c | 123 +++ .../rvv/xtheadvector/ternop_vx_constraint-5.c | 123 +++ .../rvv/xtheadvector/ternop_vx_constraint-6.c | 130 +++ .../rvv/xtheadvector/ternop_vx_constraint-7.c | 130 +++ .../rvv/xtheadvector/ternop_vx_constraint-8.c | 71 ++ .../rvv/xtheadvector/ternop_vx_constraint-9.c | 71 ++ .../rvv/xtheadvector/unop_v_constraint-1.c | 68 ++ .../riscv/rvv/xtheadvector/vlb-vsb.c | 68 ++ .../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 ++ .../riscv/rvv/xtheadvector/vlh-vsh.c | 68 ++ .../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 ++ .../riscv/rvv/xtheadvector/vlw-vsw.c | 68 ++ .../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 ++ 114 files changed, 7455 insertions(+), 457 deletions(-) create mode 100644 gcc/config/riscv/riscv_th_vector.h create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def create mode 100644 gcc/config/riscv/thead-vector.md create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fractional-type.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run-nofm.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv-nofm.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv-nofm.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-template.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vadd-zvfh-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/autovec/vand-template.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-50.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/rvv-xtheadvector.exp create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/unop_v_constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c