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[v2,0/1] RISC-V: Add RVV (RISC-V 'V' Extension) support

Message ID 20220531103356.332482-1-juzhe.zhong@rivai.ai
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Series RISC-V: Add RVV (RISC-V 'V' Extension) support | expand

Message

钟居哲 May 31, 2022, 10:33 a.m. UTC 
From: zhongjuzhe <juzhe.zhong@rivai.ai>

This patch adds implementation which missed in the V1 patch.

*** BLURB HERE ***

zhongjuzhe (1):
  Add unit-stride load store intrinsics

 .../riscv/riscv-vector-builtins-functions.cc  | 80 +++++++++++++++++++
 .../riscv/riscv-vector-builtins-functions.def |  7 ++
 .../riscv/riscv-vector-builtins-functions.h   | 42 ++++++++++
 gcc/config/riscv/riscv-vector-builtins.cc     | 14 ++++
 4 files changed, 143 insertions(+)