From patchwork Thu Nov 1 21:46:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 992088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-488856-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="T1zRcfwv"; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="CNQI2z8i"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42mJhL6MxLzB4Zx for ; Fri, 2 Nov 2018 08:47:14 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=arvaEGJRMwJ+ vaqP0BGLwigg4dTX0LZGXbazKSBlDLQ7iM5M3hgtYQzRqbMKKaKlSDOQn8Z8+K99 R+hjCcTD9Uv+wXpRfxf1mX79/TCutBM5sLQHeX420miQiLQMRY7zfYEXvRkbkUWq Vr310z/ebrh/IN/o2J8Gn8fkWlNZJoo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=fhm85kH8pTPqjqMW6c apRC+Wco8=; b=T1zRcfwvJr+QWfVDzf4h3IX2buNPkvYt56mrvTY52VZYqciBiW kwDWGnYE40Dhdp0s068ZeapvdSg4peFAyDGd0SWOGDX3qzL4/1mi5Q7i+9mMxO8m ODB82wbfEiuqtiFSZBcXwv3ejiy36bFnSfQcdE5uyrS4/FYPlHlXfKdho= Received: (qmail 48661 invoked by alias); 1 Nov 2018 21:46:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 48624 invoked by uid 89); 1 Nov 2018 21:46:55 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=atomics, iterators.md, UD:iterators.md, HX-Received:6000 X-HELO: mail-wr1-f66.google.com Received: from mail-wr1-f66.google.com (HELO mail-wr1-f66.google.com) (209.85.221.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Nov 2018 21:46:54 +0000 Received: by mail-wr1-f66.google.com with SMTP id z3-v6so2683406wru.4 for ; Thu, 01 Nov 2018 14:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=xrk6/aoUHEwG4p76IrRM8QshiifCVPdmnQEkflnL9ok=; b=CNQI2z8iDm+5c25ozGDO1pgJbgJ6gphhw1uYuIy+4V4gses+v278L2bmp+/sbxI5hB sT/zR6lChOjkWVR3R4TIbXyEY0WM7iRy934Bmeyv0S684zW8/N7Xw9l0wYtEJkWpMM0V BfAot5qJ1VC6LCXgAIma/wp4huJQs5BDMKevw= Received: from cloudburst.Home ([2a02:c7f:504f:6300:a3de:88d8:75ae:bf4c]) by smtp.gmail.com with ESMTPSA id h18-v6sm21097360wro.0.2018.11.01.14.46.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 01 Nov 2018 14:46:49 -0700 (PDT) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: ramana.radhakrishnan@arm.com, agraf@suse.de, marcus.shawcroft@arm.com, james.greenhalgh@arm.com, Richard Henderson Subject: [PATCH, AArch64, v3 0/6] LSE atomics out-of-line Date: Thu, 1 Nov 2018 21:46:42 +0000 Message-Id: <20181101214648.29432-1-richard.henderson@linaro.org> From: Richard Henderson Changes since v2: * Committed half of the patch set. * Split inline TImode support from out-of-line patches. * Removed the ST out-of-line functions, to match inline. * Moved the out-of-line functions to assembly. What I have not done, but is now a possibility, is to use a custom calling convention for the out-of-line routines. I now only clobber 2 (or 3, for TImode) temp regs and set a return value. r~ Richard Henderson (6): aarch64: Extend %R for integer registers aarch64: Implement TImode compare-and-swap aarch64: Tidy aarch64_split_compare_and_swap aarch64: Add out-of-line functions for LSE atomics aarch64: Implement -matomic-ool Enable -matomic-ool by default gcc/config/aarch64/aarch64-protos.h | 13 + gcc/common/config/aarch64/aarch64-common.c | 6 +- gcc/config/aarch64/aarch64.c | 211 ++++++++++++---- .../atomic-comp-swap-release-acquire.c | 2 +- .../gcc.target/aarch64/atomic-op-acq_rel.c | 2 +- .../gcc.target/aarch64/atomic-op-acquire.c | 2 +- .../gcc.target/aarch64/atomic-op-char.c | 2 +- .../gcc.target/aarch64/atomic-op-consume.c | 2 +- .../gcc.target/aarch64/atomic-op-imm.c | 2 +- .../gcc.target/aarch64/atomic-op-int.c | 2 +- .../gcc.target/aarch64/atomic-op-long.c | 2 +- .../gcc.target/aarch64/atomic-op-relaxed.c | 2 +- .../gcc.target/aarch64/atomic-op-release.c | 2 +- .../gcc.target/aarch64/atomic-op-seq_cst.c | 2 +- .../gcc.target/aarch64/atomic-op-short.c | 2 +- .../aarch64/atomic_cmp_exchange_zero_reg_1.c | 2 +- .../atomic_cmp_exchange_zero_strong_1.c | 2 +- .../gcc.target/aarch64/sync-comp-swap.c | 2 +- .../gcc.target/aarch64/sync-op-acquire.c | 2 +- .../gcc.target/aarch64/sync-op-full.c | 2 +- libgcc/config/aarch64/lse-init.c | 45 ++++ gcc/config/aarch64/aarch64.opt | 4 + gcc/config/aarch64/atomics.md | 185 +++++++++++++- gcc/config/aarch64/iterators.md | 3 + gcc/doc/invoke.texi | 14 +- libgcc/config.host | 4 + libgcc/config/aarch64/lse.S | 238 ++++++++++++++++++ libgcc/config/aarch64/t-lse | 44 ++++ 28 files changed, 717 insertions(+), 84 deletions(-) create mode 100644 libgcc/config/aarch64/lse-init.c create mode 100644 libgcc/config/aarch64/lse.S create mode 100644 libgcc/config/aarch64/t-lse