From patchwork Thu Jul 14 15:41:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hatim Kanchwala X-Patchwork-Id: 648443 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rr0NC0kdNz9s9Y for ; Fri, 15 Jul 2016 01:43:22 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=hatimak-me.20150623.gappssmtp.com header.i=@hatimak-me.20150623.gappssmtp.com header.b=GDFSW5a6; dkim-atps=neutral Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1bNimC-00037F-Sc; Thu, 14 Jul 2016 17:42:12 +0200 Received: from mail-pf0-f195.google.com ([209.85.192.195]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1bNilw-00036U-Dc for flashrom@flashrom.org; Thu, 14 Jul 2016 17:42:09 +0200 Received: by mail-pf0-f195.google.com with SMTP id y134so709518pfg.3 for ; Thu, 14 Jul 2016 08:41:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hatimak-me.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vcawXLLy/zkGQFPfzeEEQflQYLVPHCqv3+MPN1ou8/Q=; b=GDFSW5a6feXybzfqEHFrzJ9/qd66ueCyfkGj1BkEp5MqKa+o86s8VwPyDjTf67rG2J KmBjpuoPSsJFodiwaxbUWz0x98j+jDxZmKIpQqgD3vaDTumGNwxmz/oic8DUY+ZCdzHg /wXUGA9pMAxQt3N2/4qARG6dp4VI4ABqRO4tBppxZC8KqpQo9a8dEIR29CjeF0SW7n8k M38na0Y/2e3sbnhzYl9phDhMQ9OdC/sVg7SA/+2A3bZLHlB6RnrzH+CMADY9LNk/B7b1 Wh2hpxVDlaFYGNwCkTwwWVQkO/C9ZOPnUsygHI6E7+GUYOxc1VxO8cMemjslhkuZH+kE vwkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vcawXLLy/zkGQFPfzeEEQflQYLVPHCqv3+MPN1ou8/Q=; b=Xciw1W6vhDs6ob7nKZ7ItCDHOikEPy+UwhPJc9xunQPUHpeSORKPHBiTroTZkzg1aK 9IHyJbNaYl4zrhm2WI3dZ7WPEyEd1xDCEzsWOhN4u9GflmhHVIrV6fiCLhsygSJ3XH9I KxDu97gxG8b5Xzu1FXD7m6bu7Q9BFZ/L1gyb0NfO6ZMXsnJgx4h3kGttHX9yhnoMWm0G cPjB6AdvaCEh9mGbnYDStwLqOAlPBSXp2npKNN9ery3HARc32Rrrb902PQHBMXbiGBBx WSUtQ+gaQTOFbK+5bPiGDh6DLC7ftMgeNdP6pXSSYEZecI0/LncsiQQoILBmavjaQaIt pN0A== X-Gm-Message-State: ALyK8tKZ5xFoVy8XNbfn6eY0j0xLgtDJp6M2s1UPnmuROnCO6C/f0yclD27SQIO3wuLbAQ== X-Received: by 10.98.79.140 with SMTP id f12mr5773907pfj.161.1468510913670; Thu, 14 Jul 2016 08:41:53 -0700 (PDT) Received: from ubuntu-lenovo-z580.domain.name ([150.242.66.203]) by smtp.gmail.com with ESMTPSA id e4sm4955163pfe.69.2016.07.14.08.41.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jul 2016 08:41:53 -0700 (PDT) From: Hatim Kanchwala To: aykut.avci@barco.com Date: Thu, 14 Jul 2016 21:11:44 +0530 Message-Id: <1468510904-16763-1-git-send-email-hatim@hatimak.me> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1468503734-4248-1-git-send-email-hatim@hatimak.me> References: <1468503734-4248-1-git-send-email-hatim@hatimak.me> X-Spam-Score: -0.6 (/) Subject: Re: [flashrom] [PATCH] Print lock register configuration for N25Q128 X-BeenThere: flashrom@flashrom.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: flashrom discussion and development mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: flashrom@flashrom.org MIME-Version: 1.0 Errors-To: flashrom-bounces@flashrom.org Sender: "flashrom" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff Hi, Apologies for the previous patch, it wouldn't have worked. In haste, I had based it off an older patch I had written for AT25DF161 (a similar case). I am quite positive the following patch is correct :) Thanks :) Hatim Signed-off-by: Hatim Kanchwala --- spi25_statusreg.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 01a6862..49c7b2e 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -10,34 +10,35 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "flash.h" #include "chipdrivers.h" #include "spi.h" +#include "flashchips.h" /* === Generic functions === */ int spi_write_status_enable(struct flashctx *flash) { static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; int result; /* Send EWSR (Enable Write Status Register). */ result = spi_send_command(flash, sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) msg_cerr("%s failed\n", __func__); return result; } static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode) @@ -645,34 +646,76 @@ int spi_disable_blockprotect_n25q(struct flashctx *flash) return spi_disable_blockprotect_generic(flash, 0x5C, 1 << 7, 0, 0xFF); } int spi_prettyprint_status_register_n25q(struct flashctx *flash) { uint8_t status = spi_read_status_register(flash); spi_prettyprint_status_register_hex(status); spi_prettyprint_status_register_srwd(status); if (flash->chip->total_size <= 32 / 8 * 1024) /* N25Q16 and N25Q32: reserved */ spi_prettyprint_status_register_bit(status, 6); else msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n", (status & (1 << 6)) ? "" : "not "); msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top"); spi_prettyprint_status_register_bp(status, 2); spi_prettyprint_status_register_welwip(status); + + if (flash->chip->model_id == ST_N25Q128__3E) + { + int address, i, count, result; + uint8_t read_result, lockdown_status_sector[flash->chip->total_size / 64], cmd[4]; + cmd[0] = (uint8_t)0xE8; + + msg_cdbg("Additional information regarding block locks for %s\n", flash->chip->name); + for (address = 0x000000, i = 0, count = 0; + address < flash->chip->total_size * 1024; + address += 0x010000, i++) + { + cmd[1] = (unsigned char)(address >> 16) & 0xff; + cmd[2] = (unsigned char)(address >> 8) & 0xff; + cmd[3] = (unsigned char)address & 0xff; + result = spi_send_command(flash, sizeof(cmd), sizeof(uint8_t), cmd, &read_result); + if (result) + { + msg_cerr("%s failed during command execution (ST_N25Q128__3E)\n", __func__); + return result; + } + if (i % 8 == 0) + msg_cdbg("0x%02x:", i); + msg_cdbg(" [%s,%s]%s", + (read_result & 0x02) ? "1" : "0", + (read_result & 0x01) ? "1" : "0", + (i + 1) % 8 == 0 ? "\n": ""); + lockdown_status_sector[address / 0x010000] = read_result & 0x03; + if (read_result & 0x01) + count++; + } + + msg_cdbg("%d sector%s locked down%s", count, (count == 1) ? "" : "s", + (count == 0) ? "." : " :"); + if (count) + for (i = 0; i < ARRAY_SIZE(lockdown_status_sector); i++) + if (lockdown_status_sector[i]) + msg_cdbg(" %2d", i); + msg_cdbg("\n"); + msg_cdbg("You _may_ be able to unlock the sector%s\n", (count == 1) ? "" : "s"); + } + return 0; } /* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */ /* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */ int spi_disable_blockprotect_bp2_ep_srwd(struct flashctx *flash) { return spi_disable_blockprotect_bp2_srwd(flash); } /* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */ int spi_prettyprint_status_register_bp2_ep_srwd(struct flashctx *flash) { uint8_t status = spi_read_status_register(flash); spi_prettyprint_status_register_hex(status); spi_prettyprint_status_register_srwd(status);