From patchwork Thu Jun 29 10:46:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jose Abreu X-Patchwork-Id: 782153 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wyxGq4PYkz9s76 for ; Thu, 29 Jun 2017 20:48:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752463AbdF2KsL (ORCPT ); Thu, 29 Jun 2017 06:48:11 -0400 Received: from smtprelay.synopsys.com ([198.182.47.9]:48417 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752661AbdF2Krh (ORCPT ); Thu, 29 Jun 2017 06:47:37 -0400 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id B2D1A24E16F4; Thu, 29 Jun 2017 03:47:31 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 920DBECA; Thu, 29 Jun 2017 03:47:31 -0700 (PDT) Received: from joabreu-VirtualBox.internal.synopsys.com (joabreu-e7440.internal.synopsys.com [10.107.19.62]) by mailhost.synopsys.com (Postfix) with ESMTP id 5557BE6B; Thu, 29 Jun 2017 03:47:29 -0700 (PDT) From: Jose Abreu To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Jose Abreu , Carlos Palminha , Rob Herring , Mark Rutland , Mauro Carvalho Chehab , Hans Verkuil , Sylwester Nawrocki , devicetree@vger.kernel.org Subject: [PATCH v5 4/4] dt-bindings: media: Document Synopsys Designware HDMI RX Date: Thu, 29 Jun 2017 11:46:58 +0100 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the bindings for the Synopsys Designware HDMI RX. Signed-off-by: Jose Abreu Cc: Carlos Palminha Cc: Rob Herring Cc: Mark Rutland Cc: Mauro Carvalho Chehab Cc: Hans Verkuil Cc: Sylwester Nawrocki Cc: devicetree@vger.kernel.org Changes from v4: - Use "cfg" instead of "cfg-clk" (Rob) - Change node names (Rob) Changes from v3: - Document the new DT bindings suggested by Sylwester Changes from v2: - Document edid-phandle property --- .../devicetree/bindings/media/snps,dw-hdmi-rx.txt | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.txt diff --git a/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.txt b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.txt new file mode 100644 index 0000000..449b8a2 --- /dev/null +++ b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.txt @@ -0,0 +1,70 @@ +Synopsys DesignWare HDMI RX Decoder +=================================== + +This document defines device tree properties for the Synopsys DesignWare HDMI +RX Decoder (DWC HDMI RX). It doesn't constitute a device tree binding +specification by itself but is meant to be referenced by platform-specific +device tree bindings. + +When referenced from platform device tree bindings the properties defined in +this document are defined as follows. + +- compatible: Shall be "snps,dw-hdmi-rx". + +- reg: Memory mapped base address and length of the DWC HDMI RX registers. + +- interrupts: Reference to the DWC HDMI RX interrupt and 5v sense interrupt. + +- clocks: Phandle to the config clock block. + +- clock-names: Shall be "cfg". + +- edid-phandle: phandle to the EDID handler block. + +- #address-cells: Shall be 1. + +- #size-cells: Shall be 0. + +You also have to create a subnode for phy driver. Phy properties are as follows. + +- compatible: Shall be "snps,dw-hdmi-phy-e405". + +- reg: Shall be JTAG address of phy. + +- clocks: Phandle for cfg clock. + +- clock-names:Shall be "cfg". + +A sample binding is now provided. The compatible string is for a SoC which has +has a Synopsys DesignWare HDMI RX decoder inside. + +Example: + +dw_hdmi_soc: dw-hdmi-soc@0 { + compatible = "snps,dw-hdmi-soc"; + reg = <0x11c00 0x1000>; /* EDIDs */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + hdmi-rx@0 { + compatible = "snps,dw-hdmi-rx"; + reg = <0x0 0x10000>; + interrupts = <1 2>; + edid-phandle = <&dw_hdmi_soc>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #address-cells = <1>; + #size-cells = <0>; + + hdmi-phy@fc { + compatible = "snps,dw-hdmi-phy-e405"; + reg = <0xfc>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + }; + }; +};