From patchwork Wed May 11 22:07:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Lamparter X-Patchwork-Id: 621292 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3r4qxc34Vzz9t6Z for ; Thu, 12 May 2016 08:08:04 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.b=JHChpRX4; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752387AbcEKWIA (ORCPT ); Wed, 11 May 2016 18:08:00 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:34890 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752000AbcEKWH7 (ORCPT ); Wed, 11 May 2016 18:07:59 -0400 Received: by mail-wm0-f65.google.com with SMTP id e201so12132156wme.2; Wed, 11 May 2016 15:07:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=ur+WByahARiFwVPc+8eZSBXuDsACVeqwK1eIThtpKGg=; b=JHChpRX48D2ccRQ/Jk0/u4e0RM0YOw6L8r9OP3eb4v6gROAtky2ZH6C+Z1DDxlo4WH QCuxAcwe6+HaBrGFLq8CKArn/RZoi3d8UHT8nXNz5JYfcCf5haa6anTJjjCDAxmm2IlL gSynDlsfYtktRRcmhTo+QcPvp9L73mLTFZJ1tf8c8Nqn7G+unGvvcQb2++vNYGX5swAi BGF1agSYpOvK44Hp+ncJeidNzyFvIiLxFlv1v9guaCH694zbdsGCRBf4uTDCcD86rzzF 54BScs499x77LRUJFrSA0iL+4eBtHk3jDx1SR6gB4VPjR0ZNVTqi4DKAj/2ExV4gg0iN sTjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ur+WByahARiFwVPc+8eZSBXuDsACVeqwK1eIThtpKGg=; b=VXAxqPjXKOtvKqyQUtucQKUJaymnuoaNzfU8dx81YMk6RvtCI6KSWVA48CJtWBXoct qQbpOGgkIJvr2xJzKeZYguQyQU/ra4cIWH/sgNttWdtc7VzZ3w21Swx8kliSSYS6HLEp +5ECLo8umUIlyKDrSWqFMEqsBw4+rKp03PA+XFLRP3sTwG376Gaibazs4QPjq2WDIsc/ UDcMscaKs/NlZO7/dQXmxd8mRWHOXVO/g+9JCVhr9q4To7aIa0mvjIjP6CM8Y7xWWa8l QZr0rLK5HF6Ly1bHVCME48MiuVPTOzUy2yGsRjnyfIxXLhTodmYARGUx05qKGjip7e3Q 4+qw== X-Gm-Message-State: AOPr4FUNoWjcC4KUu+CbAFRoSBfOvz32BBqo2OFTIz+iKTawkbSSoHGnhNJhoHbdztoEzQ== X-Received: by 10.194.9.201 with SMTP id c9mr6102655wjb.7.1463004477412; Wed, 11 May 2016 15:07:57 -0700 (PDT) Received: from debian64.daheim (pD9F899E0.dip0.t-ipconnect.de. [217.248.153.224]) by smtp.googlemail.com with ESMTPSA id p129sm10523203wmd.13.2016.05.11.15.07.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 May 2016 15:07:56 -0700 (PDT) Received: from chuck by debian64.daheim with local (Exim 4.87) (envelope-from ) id 1b0cIK-0007Xc-PA; Thu, 12 May 2016 00:07:54 +0200 From: Christian Lamparter To: linux-gpio@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org Cc: Christian Lamparter , Kumar Gala , Ian Campbell , Mark Rutland , Pawel Moll , Rob Herring , Alexandre Courbot , Alistair Popple , Matt Porter , Linus Walleij Subject: [PATCH] gpio: dt-bindings: add ibm,ppc4xx-gpio binding Date: Thu, 12 May 2016 00:07:48 +0200 Message-Id: X-Mailer: git-send-email 2.8.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds binding information for IBM/AMCC/APM GPIO Controllers of the PowerPC 4XX series and compatible SoCs. The "PowerPC 405EP Embedded Processor Data Sheet" has the following to say about the GPIO controllers: " - Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses - All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. - Each GPIO outputs is separately programmable to emulate an open-drain driver (i.e. drives to zero, threestated if output bit is 1) " The ppc4xx_gpio.c driver is part of the platform/sysdev drivers in arch/powerpc/sysdev. Signed-off-by: Christian Lamparter Acked-by: Rob Herring Acked-by: Linus Walleij --- I looked into arch/powerpc/sysdev/ppc4xx_gpio.c driver and it doesn't have support for the tri-state logic (open drain is disabled), but the hardware would support it. (the #gpio-cells description suffers because of this, since the high-z option isn't there). Also there's another problem: There's no DCR pinmux driver?! So sadly, there's not much information on how to use the DCRs to control the which pin is muxed to the GPIO or to a SoC function like the i2c. This was all the valuable information I could find about the hardware, so it is included it in the binding text, even though there's no support for it... Is there anything else to add? --- .../devicetree/bindings/gpio/ibm,ppc4xx-gpio.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/ibm,ppc4xx-gpio.txt diff --git a/Documentation/devicetree/bindings/gpio/ibm,ppc4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/ibm,ppc4xx-gpio.txt new file mode 100644 index 0000000..22aabb7 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/ibm,ppc4xx-gpio.txt @@ -0,0 +1,24 @@ +* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs + +All GPIOs are pin-shared with other functions. DCRs control whether a +particular pin that has GPIO capabilities acts as a GPIO or is used for +another purpose. GPIO outputs are separately programmable to emulate +an open-drain driver. + +Required properties: + - compatible: must be "ibm,ppc4xx-gpio" + - reg: address and length of the register set for the device + - #gpio-cells: must be set to 2. The first cell is the pin number + and the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low + - gpio-controller: marks the device node as a gpio controller. + +Example: + +GPIO0: gpio@ef600b00 { + compatible = "ibm,ppc4xx-gpio"; + reg = <0xef600b00 0x00000048>; + #gpio-cells = <2>; + gpio-controller; +};