From patchwork Thu Mar 26 02:16:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leonard Crestez X-Patchwork-Id: 1261720 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48npWg65vDz9sNg for ; Thu, 26 Mar 2020 13:16:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727701AbgCZCQa (ORCPT ); Wed, 25 Mar 2020 22:16:30 -0400 Received: from inva021.nxp.com ([92.121.34.21]:52626 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727611AbgCZCQ3 (ORCPT ); Wed, 25 Mar 2020 22:16:29 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id C2FD1200776; Thu, 26 Mar 2020 03:16:26 +0100 (CET) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id B3654200775; Thu, 26 Mar 2020 03:16:26 +0100 (CET) Received: from fsr-ub1864-112.ea.freescale.net (fsr-ub1864-112.ea.freescale.net [10.171.82.98]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id A31CB203CD; Thu, 26 Mar 2020 03:16:25 +0100 (CET) From: Leonard Crestez To: Georgi Djakov , Rob Herring , Chanwoo Choi , Martin Kepplinger Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Alexandre Bailon , "Rafael J. Wysocki" , Jacky Bai , Anson Huang , Abel Vesa , Krzysztof Kozlowski , MyungJoo Ham , Kyungmin Park , Saravana Kannan , Mark Rutland , Viresh Kumar , Shawn Guo , Dong Aisheng , Fabio Estevam , Stephen Boyd , Michael Turquette , Matthias Kaehlcke , Angus Ainslie , Silvano di Ninno , linux-pm@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/8] dt-bindings: interconnect: Add bindings for imx8m noc Date: Thu, 26 Mar 2020 04:16:13 +0200 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial dt bindings for the interconnects inside i.MX chips. Multiple external IPs are involved but SOC integration means the software controllable interfaces are very similar. Main NOC node acts as interconnect provider if #interconnect-cells is present. Currently there is a single imx interconnect provider for the whole SOC. Other pieces of scalable interconnects can be present, each with their own OPP table. Signed-off-by: Leonard Crestez --- .../bindings/interconnect/fsl,imx8m-noc.yaml | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml diff --git a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml new file mode 100644 index 000000000000..6c192f1c0edd --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic i.MX bus frequency device + +maintainers: + - Leonard Crestez + +description: | + The i.MX SoC family has multiple buses for which clock frequency (and + sometimes voltage) can be adjusted. + + Some of those buses expose register areas mentioned in the memory maps as GPV + ("Global Programmers View") but not all. Access to this area might be denied + for normal (non-secure) world. + + The buses are based on externally licensed IPs such as ARM NIC-301 and + Arteris FlexNOC but DT bindings are specific to the integration of these bus + interconnect IPs into imx SOCs. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx8mn-nic + - fsl,imx8mm-nic + - fsl,imx8mq-nic + - const: fsl,imx8m-nic + - items: + - enum: + - fsl,imx8mn-noc + - fsl,imx8mm-noc + - fsl,imx8mq-noc + - const: fsl,imx8m-noc + - const: fsl, imx8m-nic + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + operating-points-v2: true + opp-table: true + + fsl,ddrc: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: + Phandle to DDR Controller. + + '#interconnect-cells': + description: + If specified then also act as an interconnect provider. Should only be + set once per soc on the main noc. + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | +#include +#include +#include + +noc: interconnect@32700000 { + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MM_CLK_NOC>; + #interconnect-cells = <1>; + + /* Used to make requests for DEV_PM_QOS_MIN_FREQUENCY: */ + fsl,scalable-node-ids = , + , + ; + fsl,scalable-nodes = <&noc>, + <&pl301_mipi>, + <&ddrc>; + + /* For passive governor: */ + devfreq = <&ddrc>; + + operating-points-v2 = <&noc_opp_table>; + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; +}; + +pl301_mipi: interconnect@32500000 { + compatible = "fsl,imx8m-nic"; + reg = <0x32500000 0x100000>; + clocks = <&clk IMX8MM_CLK_DISP_AXI>; + operating-points-v2 = <&pl301_mipi_opp_table>; + + pl301_mipi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200M { + opp-hz = /bits/ 64 <200000000>; + }; + opp-500M { + opp-hz = /bits/ 64 <500000000>; + }; + }; +}; + +ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + glock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + /* For ondemand governor: */ + devfreq-events = <&ddr_pmu>; +}; + +ddr_pmu: ddr-pmu@3d800000 { + compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; + reg = <0x3d800000 0x400000>; + interrupt-parent = <&gic>; + interrupts = ; +};