From patchwork Wed Jul 24 15:52:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Guido_G=C3=BCnther?= X-Patchwork-Id: 1136404 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sigxcpu.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45v0Gw4KqXz9s8m for ; Thu, 25 Jul 2019 01:52:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726667AbfGXPwj (ORCPT ); Wed, 24 Jul 2019 11:52:39 -0400 Received: from honk.sigxcpu.org ([24.134.29.49]:33598 "EHLO honk.sigxcpu.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726001AbfGXPwe (ORCPT ); Wed, 24 Jul 2019 11:52:34 -0400 Received: from localhost (localhost [127.0.0.1]) by honk.sigxcpu.org (Postfix) with ESMTP id 23793FB04; Wed, 24 Jul 2019 17:52:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at honk.sigxcpu.org Received: from honk.sigxcpu.org ([127.0.0.1]) by localhost (honk.sigxcpu.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id peRBQktrt7Wu; Wed, 24 Jul 2019 17:52:29 +0200 (CEST) Received: by bogon.sigxcpu.org (Postfix, from userid 1000) id 0958343419; Wed, 24 Jul 2019 17:52:26 +0200 (CEST) From: =?utf-8?q?Guido_G=C3=BCnther?= To: David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Andrzej Hajda , Neil Armstrong , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Lee Jones , =?utf-8?q?Guido_G=C3=BCnther?= , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Robert Chiras Subject: [PATCH 2/3] dt-bindings: display/bridge: Add binding for IMX NWL mipi dsi host controller Date: Wed, 24 Jul 2019 17:52:25 +0200 Message-Id: <70a5c6617936a4a095e7608b96e3f9fae5ddfbb1.1563983037.git.agx@sigxcpu.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs. Signed-off-by: Guido Günther --- .../bindings/display/bridge/imx-nwl-dsi.txt | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/imx-nwl-dsi.txt diff --git a/Documentation/devicetree/bindings/display/bridge/imx-nwl-dsi.txt b/Documentation/devicetree/bindings/display/bridge/imx-nwl-dsi.txt new file mode 100644 index 000000000000..288fdb726d5a --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/imx-nwl-dsi.txt @@ -0,0 +1,89 @@ +Northwest Logic MIPI-DSI on imx SoCs +===================================== + +NWL MIPI-DSI host controller found on i.MX8 platforms. This is a +dsi bridge for the for the NWL MIPI-DSI host. + +Required properties: +- compatible: "fsl,-nwl-dsi" + The following strings are expected: + "fsl,imx8mq-nwl-dsi" +- reg: the register range of the MIPI-DSI controller +- interrupts: the interrupt number for this module +- clock, clock-names: phandles to the MIPI-DSI clocks + The following clocks are expected on all platforms: + "core" - DSI core clock + "tx_esc" - TX_ESC clock (used in escape mode) + "rx_esc" - RX_ESC clock (used in escape mode) + "phy_ref" - PHY_REF clock. Clock is managed by the phy. Only + used to read the clock rate. +- assigned-clocks: phandles to clocks that require initial configuration +- assigned-clock-rates: rates of the clocks that require initial configuration + The following clocks need to have an initial configuration: + "tx_esc" (20 MHz) and "rx_esc" (80 Mhz). +- phys: phandle to the phy module representing the DPHY + inside the MIPI-DSI IP block +- phy-names: should be "dphy" + +Optional properties: +- power-domains phandle to the power domain +- src phandle to the system reset controller (required on + i.MX8MQ) +- mux-sel phandle to the MUX register set (required on i.MX8MQ) +- assigned-clock-parents phandles to parent clocks that needs to be assigned as + parents to clocks defined in assigned-clocks + +Example: + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30A00000 0x300>; + clocks = <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, + <&clk IMX8MQ_SYS1_PLL_266M>; + assigned-clock-rates = <80000000>, + <266000000>, + <20000000>; + interrupts = ; + power-domains = <&pgc_mipi>; + src = <&src>; + mux-sel = <&iomuxc_gpr>; + phys = <&dphy>; + phy-names = "dphy"; + status = "okay"; + + panel@0 { + compatible = "..."; + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&dcss_disp0_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + };