From patchwork Tue Oct 7 19:29:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 397400 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id F191614011B for ; Wed, 8 Oct 2014 06:31:35 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932429AbaJGT3j (ORCPT ); Tue, 7 Oct 2014 15:29:39 -0400 Received: from mail-pd0-f179.google.com ([209.85.192.179]:43889 "EHLO mail-pd0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932421AbaJGT3h (ORCPT ); Tue, 7 Oct 2014 15:29:37 -0400 Received: by mail-pd0-f179.google.com with SMTP id r10so5577930pdi.38 for ; Tue, 07 Oct 2014 12:29:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=VAecHoQcpPEhMk/+x5V9H3BNAVkWf398snWzFfDx0UE=; b=CsEn5znzl5/8lOqyhq1Mx7hxFx2CqYds7cs3li49V8op63M2yXPJ+CtOCSyAwblgMD QSH6iMKw2G2mY4J3EjgYmQ9zlAP5pvhVFDaFzPYflfdOlsKV20eHuUV6HZ2EvmQq5KOb k8p5b1LH0vlrxApCx1TfaZ/NgbsLrj4elgUv4naRiFNQzJImArTCQCE71LaDOM63a38W K3kTJl/JQLABt0jzQxZU2t5ZPa8AzpmdtYWSIMG32t530N00+7WK43cIgBAucXLRZS0t 9IGVTE68l7LdB7w8XPxvSOE+E2fW3kddK8WR+Z/8plRmwQWZQ/OInONDCujig3nzW7v1 lKMA== X-Received: by 10.70.63.67 with SMTP id e3mr5972728pds.56.1412710176646; Tue, 07 Oct 2014 12:29:36 -0700 (PDT) Received: from Alpha.gateway.2wire.net (99-189-113-45.lightspeed.sntcca.sbcglobal.net. [99.189.113.45]) by mx.google.com with ESMTPSA id oo8sm14475055pdb.86.2014.10.07.12.29.35 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Oct 2014 12:29:36 -0700 (PDT) From: Nicolin Chen To: broonie@kernel.org Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, galak@codeaurora.org Subject: [PATCH 3/8] ASoC: fsl_sai: Add indentation for binding doc to increase readability Date: Tue, 7 Oct 2014 12:29:06 -0700 Message-Id: <50d58e1906b2e3e8b9f5fded5758c69f5ca39bbc.1412708790.git.nicoleotsuka@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch refines the DT binding doc for more readability by adding extra blank lines and indentations. Signed-off-by: Nicolin Chen --- .../devicetree/bindings/sound/fsl-sai.txt | 66 ++++++++++++++-------- 1 file changed, 41 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 4956b14..044e5d7 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -5,32 +5,48 @@ which provides a synchronous audio interface that supports fullduplex serial interfaces with frame synchronization such as I2S, AC97, TDM, and codec/DSP interfaces. - Required properties: -- compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai". -- reg: Offset and length of the register set for the device. -- clocks: Must contain an entry for each entry in clock-names. -- clock-names : Must include the "bus" for register access and "mclk1" "mclk2" - "mclk3" for bit clock and frame clock providing. -- dmas : Generic dma devicetree binding as described in - Documentation/devicetree/bindings/dma/dma.txt. -- dma-names : Two dmas have to be defined, "tx" and "rx". -- pinctrl-names: Must contain a "default" entry. -- pinctrl-NNN: One property must exist for each entry in pinctrl-names. - See ../pinctrl/pinctrl-bindings.txt for details of the property values. -- big-endian: Boolean property, required if all the FTM_PWM registers - are big-endian rather than little-endian. -- lsb-first: Configures whether the LSB or the MSB is transmitted first for - the fifo data. If this property is absent, the MSB is transmitted first as - default, or the LSB is transmitted first. -- fsl,sai-synchronous-rx: This is a boolean property. If present, indicating - that SAI will work in the synchronous mode (sync Tx with Rx) which means - both the transimitter and receiver will send and receive data by following - receiver's bit clocks and frame sync clocks. -- fsl,sai-asynchronous: This is a boolean property. If present, indicating - that SAI will work in the asynchronous mode, which means both transimitter - and receiver will send and receive data by following their own bit clocks - and frame sync clocks separately. + + - compatible : Compatible list, contains "fsl,vf610-sai" or + "fsl,imx6sx-sai". + + - reg : Offset and length of the register set for the device. + + - clocks : Must contain an entry for each entry in clock-names. + + - clock-names : Must include the "bus" for register access and + "mclk1", "mclk2", "mclk3" for bit clock and frame + clock providing. + - dmas : Generic dma devicetree binding as described in + Documentation/devicetree/bindings/dma/dma.txt. + + - dma-names : Two dmas have to be defined, "tx" and "rx". + + - pinctrl-names : Must contain a "default" entry. + + - pinctrl-NNN : One property must exist for each entry in + pinctrl-names. See ../pinctrl/pinctrl-bindings.txt + for details of the property values. + + - big-endian : Boolean property, required if all the FTM_PWM + registers are big-endian rather than little-endian. + + - lsb-first : Configures whether the LSB or the MSB is transmitted + first for the fifo data. If this property is absent, + the MSB is transmitted first as default, or the LSB + is transmitted first. + + - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating + that SAI will work in the synchronous mode (sync Tx + with Rx) which means both the transimitter and the + receiver will send and receive data by following + receiver's bit clocks and frame sync clocks. + + - fsl,sai-asynchronous: This is a boolean property. If present, indicating + that SAI will work in the asynchronous mode, which + means both transimitter and receiver will send and + receive data by following their own bit clocks and + frame sync clocks separately. Note: - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the